9

©2020 Renesas Electronics Corporation

December 9, 2022

9DBL02x3/9DBL04x3/ 9DBL06x3/9DBL08x3 Datasheet

Table 4. PCIe Phase Jitter (Zero-Delay Buffer Mode)[a] [b]

[a] The Refclk jitter is measured after applying the filter functions found in PCI Express Base Specification 5.0, Revision 1.0. See the Test Loads

section of the data sheet for the exact measurement setup. The total Ref Clk jitter limits for each data rate are listed for convenience. Jitter may

be subtracted from the limit using RSS subtraction to determine remaining margin. Guaranteed by design and characterization, not 100% tested

in production.

[b] Jitter measurements shall be made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a sample rate

of 20GS/s or greater. Broadband oscilloscope noise must be minimized in the measurement. The measured PP jitter is used (no extrapolation)

for RTO measurements. Alternately, jitter measurements may be used with a Phase Noise Analyzer (PNA) extending (flat) and integrating and

folding the frequency content up to an offset from the carrier frequency of at least 200MHz (at 300MHz absolute frequency) below the Nyquist

frequency. For PNA measurements for the 2.5GT/s data rate, the RMS jitter is converted to peak to peak jitter using a multiplication factor of 8.83.

Symbol

Parameter

Conditions

Minimum Typical Maximum

Industry

Limit

Units

tjphPCIeG1-CC

PCIe Phase Jitter

(Common Clocked

Architecture)

PCIe Gen1 (2.5 GT/s), SSC < -0.5%,

any BW ZDB Mode

–

23

33

86

ps

(pk-pk)

tjphPCIeG2-CC

PCIe Gen2 Hi Band (5.0 GT/s),

SSC < -0.5%, any BW ZDB Mode

–

1.4

1.9

3.1

ps

(RMS)

PCIe Gen2 Lo Band (5.0 GT/s),

SSC < -0.5%, any BW ZDB Mode

–

0.5

0.81

3

ps

(RMS)

tjphPCIeG3-CC

PCIe Gen3 (8.0 GT/s),

SSC < -0.5%, High BW ZDB Mode

–

0.28

0.53

1

ps

(RMS)

tjphPCIeG4-CC

PCIe Gen4 (16.0 GT/s) [c] [d]

SSC < -0.5%, High BW ZDB Mode

[c] SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2MHz taking care to minimize removal of any non-SSC

content.

[d] Note that 0.7ps RMS is to be used in channel simulations to account for additional noise in a real system.

–

0.26

0.48

0.5

ps

(RMS)

tjphPCIeG5-CC

PCIe Gen5 (32.0 GT/s) [c] [e],

SSC < -0.5%, High BW ZDB Mode

[e] Note that 0.25ps RMS is to be used in channel simulations to account for additional noise in a real system.

–

0.07

0.149

0.15

ps

(RMS)

tjphPCIeG1-SRIS

PCIe Phase Jitter

(SRIS Architecture) [f]

[f] While the PCI Express Base Specification 5.0, Revision 1.0 provides the filters necessary to calculate SRIS jitter values, it does not provide

specification limits, hence the N/A in the Limit column. SRIS values are informative only. In general, a clock operating in an SRIS system must

be twice as good as a clock operating in a Common Clock system. For RMS values, twice as good is equivalent to dividing the CC value by 2.

It is up to the user to divide the clock output budget or the clock input budget by 2 to arrive at a target limit.

PCIe Gen1 (2.5 GT/s), SSC < -0.5%

High BW ZDB Mode

–

N/A

N/A

N/A

ps

(pk-pk)

tjphPCIeG2-SRIS

PCIe Gen2 (5.0 GT/s), SSC < -0.5%

High BW ZDB Mode

–

0.99

1.23

N/A

ps

(RMS)

tjphPCIeG3-SRIS

PCIe Gen3 (8.0 GT/s), SSC < -0.5%

High BW ZDB Mode

–

0.61

0.69

N/A

ps

(RMS)