LT3083MPDF datasheet(15/28 Pages) AD

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LT3083

Rev. B

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APPLICATIONS INFORMATION

Thermal Considerations

The LT3083’s internal power and thermal limiting circuitry

protects itself under overload conditions. For continuous

normal load conditions, do not exceed the 125°C maxi-

mum junction temperature. Carefully consider all sources

of thermal resistance from junction-to-ambient. This

includes (but is not limited to) junction-to-case, case-to-

heat sink interface, heat sink resistance or circuit board-

to-ambient as the application dictates. Consider all addi-

tional, adjacent heat generating sources in proximity on

the PCB.

Surface mount packages provide the necessary heat sink-

ing by using the heat spreading capabilities of the PC

board, copper traces, and planes. Surface mount heat

sinks, plated through-holes and solder-filled vias can also

spread the heat generated by power devices.

Junction-to-case thermal resistance is specified from the

IC junction to the bottom of the case directly, or the bot-

tom of the pin most directly in the heat path. This is the

lowest thermal resistance path for heat flow. Only proper

device mounting ensures the best possible thermal flow

from this area of the packages to the heat sinking material.

Note that the exposed pad of the DFN and TSSOP pack-

ages and the tab of the DD-PAK and TO-220 packages

are electrically connected to the output (VOUT).

Table 3 through Table 5 list thermal resistance as a func-

tion of copper areas on a fixed board size. All measure-

ments were taken in still air on a 4-layer FR-4 board with

1oz solid internal planes and 2oz external trace planes

with a total finished board thickness of 1.6mm. Layers

are not connected electrically or thermally.

Table 3. DF Package, 12-Lead DFN

COPPER AREA

BOARD AREA

THERMAL RESISTANCE

(JUNCTION-TO-AMBIENT)

TOPSIDE*

BACKSIDE

2500mm2

18°C/W

1000mm2

2500mm2

22°C/W

225mm2

2500mm2

29°C/W

100mm2

2500mm2

35°C/W

*Device is mounted on topside.

Table 4. FE Package, 16-Lead TSSOP

COPPER AREA

BOARD AREA

THERMAL RESISTANCE

(JUNCTION-TO-AMBIENT)

TOPSIDE*

BACKSIDE

2500mm2

16°C/W

1000mm2

2500mm2

20°C/W

225mm2

2500mm2

26°C/W

100mm2

2500mm2

32°C/W

*Device is mounted on topside.

Table 5. Q Package, 5-Lead DD-PAK

COPPER AREA

BOARD AREA

THERMAL RESISTANCE

(JUNCTION-TO-AMBIENT)

TOPSIDE*

BACKSIDE

2500mm2

13°C/W

1000mm2

2500mm2

14°C/W

125mm2

2500mm2

16°C/W

*Device is mounted on topside.

T Package, 5-Lead TO-220

Thermal Resistance (Junction-to-Case) = 3°C/W

For further information on thermal resistance and using

thermal information, refer to JEDEC standard JESD51,

notably JESD51-12.

PCB layers, copper weight, board layout and thermal vias

affect the resultant thermal resistance. Table 3 through

Table 5 provide thermal resistance numbers for best-case

4-layer boards with 1oz internal and 2oz external copper.

Modern, multilayer PCBs may not be able to achieve quite

the same level performance as found in these tables.

Calculating Junction Temperature

Example: Given an output voltage of 0.9V, a VCONTROL

voltage of 3.3V ±10%, an IN voltage of 1.5V ±5%, output

current range from 10mA to 3A and a maximum ambient

temperature of 50°C, what will the maximum junction

temperature be for the DD-PAK on a 2500mm2 board with

topside copper of 1000mm2?

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