LAN9313 datasheet(55/398 Pages) SMSC

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Three Port 10/100 Managed Ethernet Switch with MII

Datasheet

SMSC LAN9313/LAN9313i

Revision 1.2 (04-08-08)

DATASHEET

5.2.3

Ethernet PHY Interrupts

The Port 1 and Port 2 PHYs each provide a set of identical interrupt sources. The top-level PHY_INT1

(bit 26) and PHY_INT2 (bit 27) of the Interrupt Status Register (INT_STS) provides indication that a

PHY interrupt event occurre d i n the Port x PHY Interrupt Source Flags R egister

(PHY_INTERRUPT_SOURCE_x).

Port 1 and Port 2 PHY interrupts are enabled/disabled via their respective Port x PHY Interrupt Mask

via the Port x PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x). The Port 1 and

Port 2 PHYs are each capable of generating unique interrupts based on the following events:

ENERGYON Activated

Auto-Negotiation Complete

Remote Fault Detected

Link Down (Link Status Negated)

Auto-Negotiation LP Acknowledge

Parallel Detection Fault

Auto-Negotiation Page Received

In order for a Port 1 or Port 2 interrupt event to trigger the external IRQ interrupt pin, the desired PHY

interrupt event must be enabled in the corresponding Port x PHY Interrupt Mask Register

(PHY_INTERRUPT_MASK_x), the PHY_INT1(Port 1 PHY) and/or PHY_INT2(Port 2 PHY) bits of the

Interrupt Enable Register (INT_EN) must be set, and IRQ output must be enabled via bit 8 (IRQ_EN)

of the Interrupt Configuration Register (IRQ_CFG).

For additional details on the Ethernet PHY interrupts, refer to Section 7.2.8.1, "PHY Interrupts," on

page 96.

5.2.4

GPIO Interrupts

Each GPIO[11:0] of the LAN9313/LAN9313i is provided with its own interrupt. The top-level GPIO (bit

12) of the Interrupt Status Register (INT_STS) provides indication that a GPIO interrupt event occurred

in the General Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN). The General

Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN) provides enabling/disabling

and status of each GPIO[11:0] interrupt.

In order for a GPIO interrupt event to trigger the external IRQ interrupt pin, the desired GPIO interrupt

must be enabled in the General Purpose I/O Interrupt Stat us and Enable Regist er

(GPIO_INT_STS_EN), bit 12 (GPIO_EN) of the Interrupt Enable Register (INT_EN) must be set, and

IRQ output must be enabled via bit 8 (IRQ_EN) of the Interrupt Configuration Register (IRQ_CFG).

For additional details on the GPIO interrupts, refer to Section 12.2.2, "GPIO Interrupts," on page 143.

5.2.5

General Purpose Timer Interrupt

A General Purpose Timer (GPT) interrupt is provided in the top-level Interrupt Status Register

(INT_STS) and Interrupt Enable Register (INT_EN) (bit 19). This interrupt is issued when the General

Purpose Timer Configuration Register (GPT_CFG) wraps past zero to FFFFh, and is cleared when bit

19 of the Interrupt Status Register (INT_STS) is written with 1.

In order for a General Purpose Timer interrupt event to trigger the external IRQ interrupt pin, the GPT

must be enabled via the bit 29 (TIMER_EN) in the General Purpose Timer Configuration Register

(GPT_CFG), bit 19 of the Interrupt Enable Register (INT_EN) must be set, and IRQ output must be

enabled via bit 8 (IRQ_EN) of the Interrupt Configuration Register (IRQ_CFG).

For additional details on the General Purpose Timer, refer to Section 11.1, "General Purpose Timer,"

on page 141.

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