CybraTech (2000) Ltd.
SOC-3000/i Scale-On-Chip
ASIC
Technical Specification
Revision B
Page 57
July, 2002
WATCHDOG TIMER
Functions
The purpose of the watchdog timer is to
generate a CPU reset at specified intervals. If
the SOC-3000 software does not interrupt the
watchdog cycle and instead enters an
erroneous state, the watchdog time carries out
its CPU reset one second after the software
was supposed to make its interrupt. The
erroneous state may be due to a programming
error. The watchdog may be disabled or re-
triggered via its control register.
Functional Description
The operating parameters of the watchdog
timer are presented in Table 29.
TABLE 29: WATCHDOG TIMER OPERATING PARAMETERS
PARAMETER
VALUE
Time Constant
1 second
Trigger
By the control register (WDI)
Enable/Disable
By the control register (ENWD)
Power Up Mode
Disabled
Operation
The application software controls the watchdog operation. It is automatically disabled in
the In-circuit Emulator (ICE) mode and after power-up or reset.
The application software should activate the watchdog as soon as it starts normal
operation after power-on or reset conditions.
The watchdog timer should be periodically re-triggered during normal operation, before
the timer expires. Expiration of the watchdog timer resets the CPU.
If required, disabling the watchdog timer clock input can disable the watchdog.
Table 30 describes the operation of the watchdog timer.
TABLE 30: WATCHDOG TIMER COMMAND SEQUENCE
#
COMMAND
ADDRESS
BIT
SETTING
1 Enable Watchdog
C200H
3
1= Enable
0= Disable
2 Re-trigger Timer
F800H
all
FFH
3 Disable Watchdog
C200H
3
0
Control Registers Description
Setting the Clock Enable register (C200H), bit 3 to 1 enables the watchdog timer.
Setting the Clock Enable register (C200H), bit 3 to 0 disables the watchdog timer.
Writing FFH to address F800H re-triggers the watchdog.
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