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SOC-3000I Datasheet(PDF) 86 Page - List of Unclassifed Manufacturers

Part # SOC-3000I
Description  Scale-On-Chip ASIC Technical Specification Rev.B1
PDF  98 Pages
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SOC-3000I Datasheet(HTML) 86 Page - List of Unclassifed Manufacturers

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CybraTech (2000) Ltd.
SOC-3000/i Scale-On-Chip
 ASIC
Technical Specification
Revision B
Page 78
July, 2002
Load Cell Impedance
Most load cells have output impedance of 350 ohms. However, in power-restricted
applications, load cells of higher impedance, typically a 1000-ohm bridge, are used to reduce
the cell’s power consumption.
The SOC-3000 CMRR minimizes the error resulting from this high bridge impedance and
ensures full and accurate performance under this limiting condition.
The result is economical power consumption without sacrificing weighing accuracy.
Keyboard Interface
The SOC-3000 supports direct connection of a keyboard of up to 64 keys arranged in an 8 ×
8 matrix. The hardware interface with an example of a scale keyboard is shown in Figure 29.
The keyboard controller (“Keyboard Controller”, page 31) automatically scans the matrix by
asserting a high signal on the output lines (KOUT 0 to 7) and reading the input lines (KIN 0
to 7). The key hardware code, which is the code returned by the keyboard controller when
the key is pressed, is shown in Figure 12, page 31.
The keyboard controller has a programmable anti-bounce mechanism, in which different
delays can be programmed to avoid erroneous key activation due to bouncing of the keys.
The delay can be set to a discrete value from 4 to 18 milliseconds, in two-millisecond
increments. For programming the anti-bounce mechanism, see Table 14, page 32.
KIN7
KIN6
KIN5
KIN4
KIN3
KIN2
KIN1
KIN0
82
83
84
1
2
3
4
5
74
75
76
77
78
79
80
8 1
Scale Keyboard
PIN #
Signal
KOUT7
KOUT6
KOUT5
KOUT4
KOUT3
KOUT2
KOUT1
KOUT0
Bsp
7
/
4
1
.
Q
A
Z
8
*
5
2
0
W
S
X
9
-
6
3
◊
E
D
C
±
+
%
=
Enter
R
F
V
F2
F1
F3
F4
T
G
B
F5
F6
F7
F8
Esc
Y
H
N
CM
M+
O
U
J
M
CE
MR
P
I
K
L
FIGURE 29: KEYBOARD INTERFACE



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