CybraTech (2000) Ltd.
SOC-3000/i Scale-On-Chip
ASIC
Technical Specification
Revision B
Page 71
July, 2002
8051-COMPATIBLE ON-CHIP PERIPHERALS
This section describes the standard 8051 peripheral devices available to the user. These
functions are fully compatible with the standard 8051 CPUs and are controlled via the
standard 8051 Special Function Registers (SFRs).
Parallel I/O Ports
Some of the parallel I/O ports of the 80C51TBO core are available on the SOC-3000 pins.
Most of the ports are already allocated to specific functions. However, the application design
may require allocating different functions to these pins. Table 39 list the available pins,
80C51 I/O port, default function and special precaution needed when changing the function
of the pin.
TABLE 39: AVAILABLE PINS ON THE 80C51 I/O PORT
PIN #
80C51
PORT
DEFAULT
FUNCTION
SPECIAL PRECAUTIONS
7
P1.7
Buzzer
After power-up the SOC-3000 asserts 3 pulses on this pin
8
P1.5
None
9
P1.4
None
14
P3.4 /
Timer 0
None
Used in CybraTech application for power-off control in low-power
applications
15
P3.5 /
Timer 1
None
Used in CybraTech application for detecting power source
(AC/Battery)
16
P1.6
None
Used in CybraTech application to control LCD electro-luminescent
backlight operation
The I/O ports are controlled and accessible using the 80C51TBO Special Function Registers
as described in its device specification.
Timers/Counters
The 80C51 Timers/Counters external inputs are available for use on SOC-3000 pin #14
(Timer 0) and pin #15 (Timer 1). Using the timers is via the 80C51 Special Function
Registers (SFRs) as described in the 80C51TBO specification.
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