SOC-3000I datasheet(89/98 Pages) ETC2

89 / 98 page

CybraTech (2000) Ltd.

SOC-3000/i Scale-On-Chip

 ASIC

Technical Specification

Revision B

Page 81

July, 2002

Other interrupt sources may be connected to this input using open-collector drivers operating

in negative logic mode (‘0’ is active interrupt). A low voltage input triggers the INT0. The

application software applies a mechanism to determine whether the interrupt was generated

by low battery voltage or by other interrupt source.

Using Timer0 and Timer1 inputs:

SOC-3000 pin #14 is connected to the 80C51 Timer 0 input and pin #15 is connected to

Timer1 input.

These inputs may be used for counting or timer operations, or as additional interrupt inputs to

the device.

Using these inputs as interrupt inputs requires that the appropriate timer be set to 0xFE. The

next event causes the counter to increase to 0xFF and triggers the Timer 0 (or timer 1)

interrupt.

I2C-Compatible Interface

The SOC-3000 may supports a 2-wire I2C compatible serial interface. The I2C-compatible

interface shares its pins with the CPU I/O pins (P1.4, P1.5) and is implemented in software.

Table 40 provides the hardware interface information:

TABLE 40: I2C-COMPATIBLE INTERFACE HARDWARE INTERFACE

PIN#

NAME

DESCRIPTION

SDATA

Serial Data I/O pin

SCLOCK

Serial Clock pin

Power Saving Schemes

SOC-3000/i provides several means for power saving for battery-operated systems:

Set the CPU to IDLE or POWERDOWN operating modes – see detailed description in

the M8051TBO Technical Specification, Power Management section.

Disable unused hardware controllers – by disabling the controller clock via the

“Controllers Clock Enable Register (C200H)”, see tables 33 and 34.

Reduce the CPU frequency to minimum while idle by using the Frequency Controller.

The CPU frequency may be increased on the fly to 16MHz when an interrupt or an event

occurred.

Switch the power to the load cell using the I/O pins of the SOC and an external switch.

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