OR4 datasheet(45/152 Pages) LATTICE

45 / 152 page

Data Sheet

May, 2006

Lattice Semiconductor

ORCA Series 4 FPGAs

Special Function Blocks (continued)

The TAPC generates control signals that allow capture, shift, and update operations on the instruction and data

registers. In the capture operation, data is loaded into the register. In the shift operation, the captured data is

shifted out while new data is shifted in. In the update operation, either the instruction register is loaded for instruc-

tion decode, or the boundary-scan register is updated for control of outputs.

The test host generates a test by providing input into the ORCA Series TMS input synchronous with TCK. This

sequences the TAPC through states in order to perform the desired function on the instruction register or a data

TMS input value.

5-5370(F)

Figure 28. TAP Controller State Transition Diagram

SELECT-

DR-SCAN

CAPTURE-DR

SHIFT-DR

EXIT1-DR

PAUSE-DR

EXIT2-DR

UPDATE-DR

RUN-TEST/

IDLE

TEST-LOGIC-

RESET

SELECT-

IR-SCAN

CAPTURE-IR

SHIFT-IR

EXIT1-IR

PAUSE-IR

EXIT2-IR

UPDATE-IR

Boundary-Scan Cells

Figure 29 is a diagram of the boundary-scan cell (BSC)

in the ORCA series PIOs. There are four BSCs in each

PIC: one for each pad, except as noted above. The

BSCs are connected serially to form the BSR. The BSC

controls the functionality of the in, out, and 3-state sig-

nals for each I/O pad.

The BSC allows the I/O to function in either the normal

or test mode. Normal mode is deﬁned as when an out-

put buffer receives input from the PLC array and pro-

vides output at the pad or when an input buffer

provides input from the pad to the PLC array. In the test

mode, the BSC executes a boundary-scan operation,

such as shifting in scan data from an upstream BSC in

the BSR, providing test stimuli to the pad, capturing

test data at the pad, etc.

The primary functions of the BSC are shifting scan data

serially in the BSR and observing input (p_in), output

(p_out), and 3-state (p_ts) signals at the pads. The

BSC consists of three circuits: the bidirectional data

cell is used to access the input and output data, the

capture cell is used to capture the status of the I/O pad,

and the direction control cell is used to access the 3-

state value. All three cells consist of a FF used to shift

scan data which feeds a FF to control the I/O buffer.

The capture cell is connected serially to the bidirec-

tional data cell, which is connected serially to the direc-

tion control cell to form a boundary-scan shift register.

The TAPC signals (capture, update, shiftn, treset, and

TCK) and the MODE signal control the operation of the

BSC. The bidirectional data cell is also controlled by

the high out/low in (HOLI) signal generated by the

direction control cell. When HOLI is low, the bidirec-

tional data cell receives input buffer data into the BSC.

When HOLI is high, the BSC is loaded with functional

data from the PLC.

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