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HD404848FS Datasheet(PDF) 87 Page - Renesas Technology Corp |
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HD404848FS Datasheet(HTML) 87 Page - Renesas Technology Corp |
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87 / 127 page  HD404849 Series 85 Transmit Clock Error Detection (In External Clock Mode): The serial interface will malfunction if a spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. A transmit clock error of this type can be detected as shown in figure 69. If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse by noise, the octal counter reaches 000, the serial interrupt request flag (IFS: $023, bit 2) is set, and transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is entered. After the transfer completion processing is performed and IFS is reset, writing to serial mode register A (SMRA: $005) changes the state from transfer to STS wait. At this time IFS is set again, and therefore the error can be detected. |
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