4553 datasheet(16/145 Pages) RENESAS

16 / 145 page

Rev.3.02

Dec 22, 2006

page 16 of 142

REJ03B0024-0302

4553 Group

FUNCTION BLOCK OPERATIONS

CPU

(1) Arithmetic logic unit (ALU)

The arithmetic logic unit ALU performs 4-bit arithmetic such as 4-

bit data addition, comparison, AND operation, OR operation, and

bit manipulation.

(2) Register A and carry flag

change, and I/O operation.

Carry flag CY is a 1-bit flag that is set to “1” when there is a carry

with the AMC instruction (Figure 1).

It is unchanged with both A n instruction and AM instruction. The value

of A0 is stored in carry flag CY with the RAR instruction (Figure 2).

Carry flag CY can be set to “1” with the SC instruction and cleared

to “0” with the RC instruction.

(3) Registers B and E

data, and for 8-bit data transfer together with register A.

with register B used as the high-order 4 bits and register A as the

low-order 4 bits (Figure 3).

turned from the power down mode. Accordingly, set the initial value.

(4) Register D

It is used to store a 7-bit ROM address together with register A and

is used as a pointer within the specified page when the TABP p,

BLA p, or BMLA p instruction is executed (Figure 4).

Also, when the TABP p instruction is executed at UPTF flag = “1”,

the high-order 2 bits of ROM reference data is stored to the low-or-

der 2 bits of register D, the high-order 1 bit of register D is “0”.

When the TABP p instruction is executed at UPTF flag = “0”, the

contents of register D remains unchanged. The UPTF flag is set to

“1” with the SUPT instruction and cleared to “0” with the RUPT in-

struction. The initial value of UPTF flag is “0”.

turned from the power down mode. Accordingly, set the initial value.

Fig. 1 AMC instruction execution example

Fig. 2 RAR instruction execution example

Fig. 3 Registers A, B and register E

Fig. 4 TABP p instruction execution example

(CY)

(M(DP))

(A)

Addition

ALU

<Carry>

A3 A2 A1 A0

CYA3 A2 A1

RAR instruction

<Set>

SC instruction

<Clear>

RC instruction

A3 A2 A1 A0

B3 B2 B1 B0

E7 E6 E5 E4 E3 E2 E1 E0

A3 A2 A1 A0

B3 B2 B1 B0

TAB instruction

TEAB instruction

TABE instruction

TBA instruction

Specifying address

TABP p instruction

p6 p5 p4 p3 p2 p1 p0

PCH

DR2 DR1DR0 A3 A2 A1 A0

PCL

Immediate field

value p

The contents of

ROM

Middle-order 4 bits

Low-order 4bits

The contents of

High-order 2 bits

* UPTF=1, high-order 1 bit of register D is “0”.

UPTF=0, data is not transferred to register D.

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