7516 datasheet(83/90 Pages) RENESAS

83 / 90 page

Rev.1.01

Jul 01, 2003

page 83 of 89

7516 Group

TIMING REQUIREMENTS

Table 29 Timing requirements (1)

(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

Reset input “L” pulse width

External clock input cycle time

External clock input “H” pulse width

External clock input “L” pulse width

CNTR0, CNTR1 input cycle time

CNTR0, CNTR1 input “H” pulse width

CNTR0, CNTR1 input “L” pulse width

INT0 to INT3 input “H” pulse width

INT0 to INT3 input “L” pulse width

Serial I/O1 clock input cycle time (Note)

Serial I/O1 clock input “H” pulse width (Note)

Serial I/O1 clock input “L” pulse width (Note)

Serial I/O1 clock input set up time

Serial I/O1 clock input hold time

Serial I/O2 clock input cycle time

Serial I/O2 clock input “H” pulse width

Serial I/O2 clock input “L” pulse width

Serial I/O2 clock input set up time

Serial I/O2 clock input hold time

tW(RESET)

tC(XIN)

tWH(XIN)

tWL(XIN)

tC(CNTR)

tWH(CNTR)

tWL(CNTR)

tWH(INT)

tWL(INT)

tC(SCLK1)

tWH(SCLK1)

tWL(SCLK1)

tsu(RxD-SCLK1)

th(SCLK1-RxD)

tC(SCLK2)

tWH(SCLK2)

tWL(SCLK2)

tsu(SIN2-SCLK2)

th(SCLK2-SIN2)

Limits

XIN cycles

Parameter

Min.

125

200

800

370

220

100

1000

400

200

Typ.

Max.

Symbol

Unit

Note : When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous).

Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).

Table 30 Timing requirements (2)

(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)