7516 datasheet(27/90 Pages) RENESAS

27 / 90 page

Rev.1.01

Jul 01, 2003

page 27 of 89

7516 Group

Fig. 24 Block diagram of Serial I/O2

Fig. 25 Timing chart of Serial I/O2

Transfer clock (Note 1)

Serial I/O2 output SOUT2

Serial I/O2 input SIN2

Receive enable signal SRDY2

Write-in signal to

serial I/O2 register

(Note 2)

Serial I/O2 interrupt request bit set

1: When the internal clock is selected as a transfer clock, the f(XIN) clock division (f(XCIN) in low-speed mode) can be selected

by setting bits 0 to 2 of serial I/O2 control register 1.

2: When the internal clock is selected as a transfer clock, the SOUT2 pin has high impedance after transfer completion.

Notes

XIN

“1”

“0”

“1”

“0”

“1”

SRDY2

“0”

“1”

1/8

1/16

1/32

1/64

1/128

1/256

“1”

“0”

XCIN

“10”

“00”

“01”

Data bus

Serial I/O2

interrupt request

Serial I/O2 port selection bit

Serial I/O counter 2 (3)

Serial I/O2 register (8)

Synchronous circuit

Serial I/O2 port selection bit

Serial I/O2 synchronous

clock selection bit

SRDY2 output enable bit

External clock

Internal synchronous

clock selection bits

Optional transfer bits (3)

P02/SCLK2

P01/SOUT2

P00/SIN2

P02 latch

P01 latch

P03 latch

P03/SRDY2

P43/SCMP2/INT2

Serial I/O2 I/O comparison

signal control bit

P43 latch

Main clock division ratio

selection bits (Note)

Note: Either high-speed, middle-speed or low-speed mode is selected by bits 6 and 7 of CPU mode register.

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