7516 datasheet(85/90 Pages) RENESAS

85 / 90 page

Rev.1.01

Jul 01, 2003

page 85 of 89

7516 Group

Symbol

Parameter

Unit

MULTI-MASTER I2C-BUS BUS LINE CHARACTERISTICS

Table 33 Multi-master I2C-BUS bus line characteristics

Bus free time

Hold time for START condition

Hold time for SCL clock = “0”

Rising time of both SCL and SDA signals

Data hold time

Hold time for SCL clock = “1”

Falling time of both SCL and SDA signals

Data setup time

Setup time for repeated START condition

Setup time for STOP condition

tBUF

tHD;STA

tLOW

tHD;DAT

tHIGH

tSU;DAT

tSU;STA

tSU;STO

Min.

Max.

Min.

Max.

µs

Standard clock mode

High-speed clock mode

Note: Cb = total capacitance of 1 bus line

Fig. 78 Timing diagram of multi-master I2C-BUS

4.7

4.0

4.7

4.0

250

4.7

4.0

1000

300

1.3

0.6

1.3

20+0.1Cb

0.6

20+0.1Cb

100

0.6

300

0.9

300

tBUF

tHD:STA

tHD:DAT

tLOW

tHIGH

tsu:DAT

tsu:STA

tHD:STA

tsu:STO

SCL

SDA

S : START condition

Sr : RESTART condition

P : STOP condition

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