SH7243 datasheet(37/1726 Pages) RENESAS

37 / 1726 page

Section 1 Overview

Rev. 1.00 Jun. 26, 2008 Page 7 of 1692

REJ09B0393-0100

Items

Specification

A/D converter

• Three modules (SH7286)

Two modules (SH7285 and SH7243)

• 12-bit resolution

• Eight input channels (SH7285 and SH7243) and twelve input channels

(SH7286)

• Sampling can be carried out simultaneously on three channels.

• A/D conversion request by the external trigger or timer trigger

D/A converter

(only in SH7286)

• 8-bit resolution

• Two output channels

ASE break controller

(ABC)

• Ten break channels

• The cycle of the internal bus can be set as break conditions

User break controller

(UBC)

• Four break channels

• Addresses, data values, type of access, and data size can all be set as

break conditions

User debugging

interface (H-UDI)

• E10A emulator support

• JTAG-standard pin assignment

• Realtime branch trace

Advanced user

debugger (AUD)

• Six input/output pins

• Branch source address/destination address trace

• Window data trace

• Full trace

All trace data can be output by interrupting CPU operation

• Realtime trace

Trace data can be output within the range where CPU operation is not

interrupted

On-chip ROM

• 256 Kbytes, 512 Kbytes, 768 Kbytes, or 1 Mbyte

On-chip RAM

• Four pages

• 32 Kbytes (SH7286, SH7285)

• 24 Kbytes (SH7286, SH7285)

• 12 Kbytes (SH7243)

• 8 Kbytes (SH7243)

Power supply voltage

• VCC: 3.0 to 3.6 V or 4.5 to 5.5 V

• AVCC: 4.5 to 5.5 V

SH7243 Datasheet(PDF) 37 Page - Renesas Technology Corp

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