SH7243 datasheet(45/1726 Pages) RENESAS

45 / 1726 page

Section 1 Overview

Rev. 1.00 Jun. 26, 2008 Page 15 of 1692

REJ09B0393-0100

Classification

Symbol

I/O

Name

Function

NMI

Input

Non-maskable

interrupt

Non-maskable interrupt request pin.

Fix it high when not in use.

IRQ7 to IRQ0

Input

Interrupt

requests 7 to 0

Maskable interrupt request pins.

Level-input or edge-input detection

can be selected. When the edge-input

detection is selected, the rising edge,

falling edge, or both edges can also

be selected.

Interrupts

IRQOUT

Output Interrupt request

output

Indicates that an interrupt has

occurred, enabling external devices to

be informed of an interrupt occurrence

even while the bus mastership is

released.

Address bus

A25 to A0

Output Address bus

Outputs addresses. (A25 to A21 are

available only in the SH7286.)

Data bus

D31 to D0

I/O

Data bus

Bidirectional data bus. (D31 to D16

are available only in the SH7286.)

Bus control

CS7 to CS0

Output Chip select 7

to 0

Chip-select signals for external

memory or devices.

Output Read

Indicates that data is read from an

external device.

RD/

Output Read/write

Read/write signal.

Output Bus start

Bus-cycle start signal.

Output Address hold

Address hold timing signal for the

device that uses the address/data-

multiplexed bus.

FRAME

Output Frame signal

In burst MPX-I/O interface mode,

negated before the last bus cycle to

indicate that the next bus cycle is the

last access (only in SH7286)

WAIT

Input

Wait

Input signal for inserting a wait cycle

into the bus cycles during access to

the external space.

WRHH

Output Write to HH byte Indicates a write access to bits 31 to

24 of data of external memory or

device (only in SH7286).

WRHL

Output Write to HL byte Indicates a write access to bits 23 to

16 of data of external memory or

device (only in SH7286).

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