SH7243 datasheet(46/1726 Pages) RENESAS

46 / 1726 page

Section 1 Overview

Rev. 1.00 Jun. 26, 2008 Page 16 of 1692

REJ09B0393-0100

Classification

Symbol

I/O

Name

Function

WRH

Output

Write to upper

byte

Indicates a write access to bits 15 to 8

of data of external memory or device.

WRL

Output

Write to lower

byte

Indicates a write access to bits 7 to 0

of data of external memory or device.

DQMUU

Output

HH byte

selection

Selects bits D31 to D24 when SDRAM

is connected (only in SH7286).

DQMUL

Output

HL byte

selection

Selects bits D23 to D16 when SDRAM

is connected (only in SH7286).

DQMLU

Output

Upper byte

selection

Selects bits D15 to D8 when SDRAM

is connected.

DQMLL

Output

Lower byte

selection

Selects bits D7 to D0 when SDRAM is

connected.

RASU

Output

RAS

Connected to the

RAS pin when

SDRAM is connected (only in

SH7286).

CASU

Output

CAS

Connected to the

CAS pin when

SDRAM is connected (only in

SH7286).

RASL

Output

RAS

Connected to the

RAS pin when

SDRAM is connected.

CASL

Output

CAS

Connected to the

CAS pin when

SDRAM is connected.

CKE

Output

CK enable

Connected to the CKE pin when

SDRAM is connected.

Bus control

REFOUT

Output

Refresh request

output

Request signal output for refresh

execution while the bus mastership is

released.

DREQ0 to

DREQ3

Input

DMA-transfer

request

Input pins to receive external requests

for DMA transfer (DREQ2 and DREQ3

are only in SH7286).

DACK0 to

DACK3

Output

DMA-transfer

request accept

Output pins for signals indicating

acceptance of external requests from

external devices (DACK2 and DACK3

are only in SH7286).

Direct memory

access controller

(DMAC)

TEND1,

TEND0

Output

DMA-transfer

end output

Output pins for DMA transfer end.

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