SH7243 datasheet(14/1726 Pages) RENESAS

14 / 1726 page

Rev. 1.00 Jun. 26, 2008 Page xiv of xxx

8.9

Usage Notes ...................................................................................................................... 242

8.9.1

Module Standby Mode Setting ......................................................................... 242

8.9.2

On-Chip RAM .................................................................................................. 242

8.9.3

DTCE Bit Setting.............................................................................................. 242

8.9.4

Chain Transfer .................................................................................................. 242

8.9.5

Transfer Information Start Address, Source Address, and Destination Address242

8.9.6

Access to DTC Registers through DTC............................................................ 243

8.9.7

Notes on IRQ Interrupt as DTC Activation Source .......................................... 243

8.9.8

Note on SCI or SCIF as DTC Activation Sources ............................................ 243

8.9.9

Clearing Interrupt Source Flag.......................................................................... 243

8.9.10

Conflict between NMI Interrupt and DTC Activation ...................................... 243

8.9.11

Note on USB as DTC Activation Sources ........................................................ 243

8.9.12

Operation when a DTC Activation Request has been Cancelled...................... 244

Section 9 Bus State Controller (BSC) ................................................................. 245

9.1

Features............................................................................................................................. 245

9.2

Input/Output Pins.............................................................................................................. 248

9.3

Area Overview.................................................................................................................. 250

9.3.1

Address Map..................................................................................................... 250

9.3.2

Setting Operating Modes .................................................................................. 253

9.4

Register Descriptions........................................................................................................ 255

9.4.1

Common Control Register (CMNCR) .............................................................. 256

9.4.2

CSn Space Bus Control Register (CSnBCR) (n = 0 to 7) ................................. 259

9.4.3

CSn Space Wait Control Register (CSnWCR) (n = 0 to 7) .............................. 264

9.4.4

SDRAM Control Register (SDCR)................................................................... 293

9.4.5

Refresh Timer Control/Status Register (RTCSR)............................................. 297

9.4.6

Refresh Timer Counter (RTCNT)..................................................................... 299

9.4.7

Refresh Time Constant Register (RTCOR) ...................................................... 300

9.4.8

Bus Function Extending Register (BSCEHR) .................................................. 301

9.5

Operation .......................................................................................................................... 305

9.5.1

Endian/Access Size and Data Alignment.......................................................... 305

9.5.2

Normal Space Interface .................................................................................... 310

9.5.3

Access Wait Control ......................................................................................... 315

9.5.4

CSn Assert Period Expansion ........................................................................... 317

9.5.5

MPX-I/O Interface............................................................................................ 318

9.5.6

SDRAM Interface ............................................................................................. 322

9.5.7

Burst ROM (Clock Asynchronous) Interface ................................................... 359

9.5.8

SRAM Interface with Byte Selection ............................................................... 362

9.5.9

Burst ROM (Clock Synchronous) Interface...................................................... 367

9.5.10

Wait between Access Cycles ............................................................................ 368

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