7906 datasheet(89/531 Pages) RENESAS

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7906 Group User’s Manual Rev.2.0

INTERRUPTS

6-10

6.5 Interrupt priority level detection circuit

The interrupt priority level detection circuit is used to select the interrupt with the highest priority level from

multiple interrupt requests sampled at the same timing. Figure 6.5.1 shows the interrupt priority level detection

circuit.

6.5 Interrupt priority level detection circuit

Fig. 6.5.1 Interrupt priority level detection circuit

IPL

Processor interrupt priority level

Interrupt with the highest priority level

Acceptance of interrupt request

Watchdog timer interrupt

Reset

Interrupt disable flag (I)

Level 0 (Initial value)

Interrupt priority level

A-D conversion

INT4

INT3

Timer A2

Timer A1

Timer A0

Interrupt priority level

Timer A4

Timer A3

UART1 transmit

UART1 receive

UART0 transmit

UART0 receive

Timer B2

Timer B1

Timer B0

INT6

INT5

INT7

Timer A5

Timer A6

Timer A7

Timer A8

Timer A9

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