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HARDWARE

1.11 Interrupts

7470/7471/7477/7478 GROUP USER’S MANUAL

1-56

(1) Interrupt request bit

The interrupt request bits are assigned to each bit of the Interrupt request register 1(IR1: Address

00FC16) and the Interrupt request register 2(IR2: Address 00FD16).

If an interrupt request occurs, the corresponding interrupt request bit is set to “1.”

The interrupt request bit is held in the “1” state until the interrupt is accepted. After it is accepted,

this bit is automatically cleared to “0.”

The interrupt request bit can be cleared to “0” by software but cannot be set to “1” by software.

(2) Interrupt enable bit

The interrupt enable bits are assigned to each bit of the Interrupt control register 1 (IE1: Address

00FE16) and the Interrupt control register 2 (IE2: Address 00FF16).

The interrupt enable bit controls the acceptance of the corresponding interrupt. When the interrupt

enable bit is “0,” the acceptance of the corresponding interrupt is disabled. If an interrupt request

occurs when this bit is “0,” the corresponding interrupt request bit is set to “1,” but this interrupt is

not accepted. In this case, the interrupt request bit is cleared to “0” by software or remains in the

“1” state until the interrupt enable bit is set to “1.”

When an interrupt enable bit is “1,” the corresponding interrupt is enabled. If an interrupt request

occurs when this bit is “1,” this interrupt is accepted. (However, the interrupt disable flag that will be

described later must be “0.”) The interrupt enable bit can be cleared to “0” or set to “1” by software.

(3) Interrupt disable flag

The interrupt disable flag controls the acceptance of the interrupt, and is assigned to bit 2 of the

Processor status register (PS).

When this flag is “1,” the interrupt disable state is provided. When this flag is “0,” the acceptance of

interrupt is enable state.

This flag is set to “1” by the SEI instruction and cleared to “0” by the CLI instruction.

This flag is set to “1” (interrupt disable state) automatically after the interrupt processing routine. To

use a multi-interrupt, set this flag to “0” by using the CLI instruction in the interrupt processing

routine.

2 Interrupt setting

Set an interrupt according to the procedure shown below.

1The interrupt disable flag is set to “1.”

2The interrupt enable bit is cleared to “0.”

3For the INT interrupt or the CNTR interrupt, set the active edge in the Edge polarity selection

Select one of the above interrupts in bit 4 of the Edge polarity selection register because the

CNTR0 interrupt and the CNTR1 interrupt can not be used simultaneously. ( 0: CNTR0, 1:

CNTR1 )

4The request bit of interrupt used is cleared to “0.” (Refer to “Table 1.11.2.”)

5The enable bit of interrupt used is set to “1.” (Refer to “Table 1.11.2.”)

6The interrupt disable flag is cleared to “0.”

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