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AD9716-EBZ Datasheet(PDF) 45 Page - Analog Devices

Part # AD9716-EBZ
Description  Dual, 8-/10-/12-/14-Bit Low Power Digital-to-Analog Converters
PDF  48 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9716-EBZ Datasheet(HTML) 45 Page - Analog Devices

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AD9714/AD9715/AD9716/AD9717
Rev. 0 | Page 45 of 48
Two registers are assigned to each DAC with 10 bits for the
actual DAC current to be generated, a 3-bit offset (and gain)
adjustment, a 2-bit current range adjustment, and an enable/
disable bit. Setting the QAUXOFS and IAUXOFS bits to all 1s
disables the respective op amp and routes the DAC current
directly to their respective FSADJI/ AUXI or FSADJQ/AUXQ
pins. This is especially useful where the loads to be driven are
beyond the limited capability of the on-chip amplifier. The
DAC output will open circuit when not enabled (QAUXEN
or IAUXEN = 0).
DAC-TO-MODULATOR INTERFACING
The auxiliary DACs can be used for local oscillator (LO) cancella-
tion when the DAC output is followed by a quadrature modulator.
This LO feedthrough is caused by the input referred dc offset
voltage of the quadrature modulator (and the DAC output offset
voltage mismatch) and can degrade system performance. Typical
DAC-to-quadrature modulator interfaces are shown in Figure 94
and Figure 95. Often, the input common-mode voltage for the
modulator is much higher than the output compliance range of
the DAC, so that ac coupling or a dc level shift is necessary. If the
required common-mode input voltage on the quadrature modu-
lator matches that of the DAC, the dc blocking capacitors in
Figure 94 can be removed. A low-pass or band-pass passive filter
is recommended when spurious signals from the DAC (distortion
and DAC images) at the quadrature modulator inputs can affect
the system performance. Placing the filter at the location shown
in Figure 94 and Figure 95 allows easy design of the filter, because
the source and load impedances can easily be designed close to
500 Ω for a 2 mA full-scale output.
AD9714/AD9715/
AD9716/AD9717
AUXDAC1
AD9714/AD9715/
AD9716/AD9717
I DAC
100kΩ
OPTIONAL
PASSIVE
FILTERING
MODULATOR V+
QUADRATURE
MODULATOR
I INPUTS
AD9714/AD9715/
AD9716/AD9717
AUX2DAC
AD9714/AD9715/
AD9716/AD9717
Q DAC
100kΩ
OPTIONAL
PASSIVE
FILTERING
MODULATOR V+
QUADRATURE
MODULATOR
Q INPUTS
Figure 94. Typical Use of Auxiliary DACs and On-Chip Resistors for Direct
Coupling to Quadrature Modulators
AD9714/AD9715/
AD9716/AD9717
AUXDAC
AD9714/AD9715/
AD9716/AD9717
I OR Q DAC
100kΩ
1kΩ
OPTIONAL
PASSIVE
FILTERING
ADL537x FAMILY
I OR Q INPUTS
Figure 95. Typical Use of Auxiliary DACs When DC Coupling to Quadrature
Modulator ADL537x Family
CORRECTING FOR NONIDEAL PERFORMANCE OF
QUADRATURE MODULATORS ON THE IF-TO-RF
CONVERSION
Analog quadrature modulators make it very easy to realize
single sideband radios. However, there are several nonideal
aspects of quadrature modulator performance. Among these
analog degradations are gain mismatch and LO feedthrough.
Gain Mismatch
The gain in the real and imaginary signal paths of the quad-
rature modulator may not be matched perfectly. This leads
to less than optimal image rejection because the cancellation of
the negative frequency image is less than perfect.
LO Feedthrough
The quadrature modulator has a finite dc referred offset, as well
as coupling from its LO port to the signal inputs. These can lead
to a significant spectral spur at the frequency of the Quadrature
Modulator LO.
The AD9714/AD9715/AD9716/AD9717 have the capability
to correct for both of these analog degradations. However,
understand that these degradations drift over temperature;
therefore, if close to optimal single sideband performance
is desired, a scheme for sensing these degradations over
temperature and correcting them may be necessary.
I/Q CHANNEL GAIN MATCHING
Fine gain matching is achieved by adjusting the values in the
DAC fine gain adjustment registers. For the I DAC, these values
are in the I DAC gain register (Register 0x03). For the Q DAC,
these values are in the Q DAC gain register (Register 0x06). These
are 6-bit values that cover ±2% of full scale. To perform gain
compensation starting from the default values of zero, raise the
value of one of these registers a few steps until it can be deter-
mined if the amplitude of the unwanted image is increased or
decreased. If the unwanted image increased in amplitude, remove
the step and try the same adjustment on the other DAC control
register. Iterate register changes until the rejection cannot be
improved further. If the fine gain adjustment range is not sufficient
to find a null (that is, the register goes full scale with no null
apparent) adjust the course gain settings of the two DACs
accordingly and try again. Variations on this simple method
are possible.



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