MSP430F2002IPWR datasheet(7/88 Pages) TI

7 / 88 page

MSP430x20x1, MSP430x20x2, MSP430x20x3

MIXED SIGNAL MICROCONTROLLER

SLAS491D -- AUGUST 2005 -- REVISED SEPTEMBER 2007

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Terminal Functions, MSP430x20x1

TERMINAL

NAME

PW or N

RSA

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

P1.0/TACLK/ACLK/CA0

I/O

General-purpose digital I/O pin

Timer_A, clock signal TACLK input

ACLK signal ouput

Comparator_A+, CA0 input

P1.1/TA0/CA1

I/O

General-purpose digital I/O pin

Timer_A, capture: CCI0A input, compare: Out0 output

Comparator_A+, CA1 input

P1.2/TA1/CA2

I/O

General-purpose digital I/O pin

Timer_A, capture: CCI1A input, compare: Out1 output

Comparator_A+, CA2 input

P1.3/CAOUT/CA3

I/O

General-purpose digital I/O pin

Comparator_A+, output / CA3 input

P1.4/SMCLK/C4/TCK

I/O

General-purpose digital I/O pin

SMCLK signal output

Comparator_A+, CA4 input

JTAG test clock, input terminal for device programming and test

P1.5/TA0/CA5/TMS

I/O

General-purpose digital I/O pin

Timer_A, compare: Out0 output

Comparator_A+, CA5 input

JTAG test mode select, input terminal for device programming and test

P1.6/TA1/CA6/TDI/TCLK

I/O

General-purpose digital I/O pin

Timer_A, compare: Out1 output

Comparator_A+, CA6 input

JTAG test data input or test clock input during programming and test

P1.7/CAOUT/CA7/TDO/TDI†

I/O

General-purpose digital I/O pin

Comparator_A+, output / CA7 input

JTAG test data output terminal or test data input during programming and

test

XIN/P2.6/TA1

I/O

Input terminal of crystal oscillator

General-purpose digital I/O pin

Timer_A, compare: Out1 output

XOUT/P2.7

I/O

Output terminal of crystal oscillator

General-purpose digital I/O pin

RST/NMI/SBWTDIO

Reset or nonmaskable interrupt input

Spy-Bi-Wire test data input/output during programming and test

TEST/SBWTCK

Selects test mode for JTAG pins on Port1. The device protection fuse is

connected to TEST.

Spy-Bi-Wire test clock input during programming and test

VCC

Supply voltage

VSS

Ground reference

13, 15

Not connected

QFN Pad

Package

Pad

QFN package pad connection to VSS recommended.

† TDO or TDI is selected via JTAG instruction.

NOTE: If XOUT/P2.7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection

to this pad after reset.

MSP430F2002IPWR Datasheet(PDF) 7 Page - Texas Instruments

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