PCI1221 datasheet(47/123 Pages) TI

47 / 123 page

PCI1221 GHK/PDV

PC CARD CONTROLLERS

SCPS042 – JULY 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

status register

Bit

Name

Status

Type

R/C

Default

Status

Type:

Read only, read/clear (see individual bit descriptions)

Offset:

06h (functions 0, 1)

Default:

0210h

Description: The status register provides device information to the host system. Bits in this register may be

read normally. A bit in the status register is reset when a 1 is written to that bit location; a 0

written to a bit location has no effect. All bit functions adhere to the definitions in the PCI Local

Bus Specification 2.2. PCI bus status is shown through each function. See Table 17 for the

complete description of the register contents.

Table 17. Status Register

BIT

SIGNAL

TYPE

FUNCTION

PAR_ERR

R/C

Detected parity error. Bit 15 is set when a parity error is detected (either address or data).

SYS_ERR

R/C

Signaled system error. Bit 14 is set when SERR is enabled and the PCI1221 signals a system error to the

host.

MABORT

R/C

Received master abort. Bit 13 is set when a cycle initiated by the PCI1221 on the PCI bus has been

terminated by a master abort.

TABT_REC

R/C

Received target abort. Bit 12 is set when a cycle initiated by the PCI1221 on the PCI bus was terminated

by a target abort.

TABT_SIG

R/C

Signaled target abort. Bit 11 is set by the PCI1221 when it terminates a transaction on the PCI bus with

a target abort.

10–9

PCI_SPEED

DEVSEL timing. These read-only bits encode the timing of DEVSEL and are hardwired 01b, indicating that

the PCI1221 asserts PCI_SPEED at a medium speed on nonconfiguration cycle accesses.

DATAPAR

R/C

Data parity error detected.

0 = The conditions for setting bit 8 have not been met.

1 = A data parity error occurred, and the following conditions were met:

a. PERR was asserted by any PCI device including the PCI1221.

b. The PCI1221 was the bus master during the data parity error.

c. The parity error response bit is set in the command.

FBB_CAP

Fast back-to-back capable. The PCI1221 cannot accept fast back-to-back transactions; thus, bit 7 is

hardwired to 0.

UDF

User-definable feature support. The PCI1221 does not support the user-definable features; thus, bit 6 is

hardwired to 0.

66MHZ

66-MHz capable. The PCI1221 operates at a maximum PCLK frequency of 33 MHz; therefore, bit 5 is

hardwired to 0.

CAPLIST

Capabilities list. Bit 4 is read only and returns 1 when read. This bit indicates that capabilities in addition

to standard PCI capabilities are implemented. The linked list of PCI power-management capabilities is

implemented in this function.

3–0

RSVD

Reserved. Bits 3–0 return 0s when read.

PCI1221 Datasheet(PDF) 47 Page - Texas Instruments

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