PCI1221 datasheet(99/123 Pages) TI

99 / 123 page

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

ExCA memory window 0–4 offset-address high-byte register (index 15h, 1Dh, 25h, 2Dh, 35h)

Bit

Name

ExCA memory window 0–4 offset-address high byte

Type

R/W

Default

ExCA memory window 0 offset-address high byte

Offset:

CardBus socket address + 815h; Card A ExCA offset 15h

Card B ExCA offset 55h

ExCA memory window 1 offset-address high byte

Offset:

CardBus socket address + 81Dh; Card A ExCA offset 1Dh

Card B ExCA offset 5Dh

ExCA memory window 2 offset-address high byte

Offset:

CardBus socket address + 825h; Card A ExCA offset 25h

Card B ExCA offset 65h

ExCA memory window 3 offset-address high byte

Offset:

CardBus socket address + 82Dh; Card A ExCA offset 2Dh

Card B ExCA offset 6Dh

ExCA memory window 4 offset-address high byte

Offset:

CardBus socket address + 835h; Card A ExCA offset 35h

Card B ExCA offset 75h

Type:

Read only, read/write (see individual bit descriptions)

Default:

00h

Size:

One byte

Description: These registers contain the high six bits of the 16-bit memory window offset address for

memory windows 0, 1, 2, 3 and 4. The lower six bits of these registers correspond to bits

A25-A20 of the offset address. In addition, the write protection and common/attribute memory

configurations are set in this register. See Table 49 for a complete description of the register

contents.

Table 49. ExCA Memory Window 0–4 Offset-Address High-Byte Register (Index 15h, 1Dh, 25h, 2Dh, 35h)

BIT

SIGNAL

TYPE

FUNCTION

WINWP

R/W

Write protect. Bit 7 specifies whether write operations to this memory window are enabled. This bit is

encoded as:

0 = Write operations are allowed (default).

1 = Write operations are not allowed.

REG

R/W

Bit 6 specifies whether this memory window is mapped to card attribute or common memory. This bit is

encoded as:

0 = Memory window is mapped to common memory (default).

1 = Memory window is mapped to attribute memory.

5-0

OFFHB

R/W

Offset-address high byte. Bits 5-0 represent the upper address bits A25-A20 of the memory window

offset address.

PCI1221 Datasheet(PDF) 99 Page - Texas Instruments

PCI1221 Datasheet(HTML) 99 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL