PCI1221 datasheet(102/123 Pages) TI

102 / 123 page

102

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

ExCA global-control register (index 1Eh)

Bit

Name

ExCA global control

Type

R/W

Default

ExCA global control

Type:

Read only, read/write (see individual bit descriptions)

Offset:

CardBus socket address + 81Eh; Card A ExCA offset 1Eh

Card B ExCA offset 5Eh

Default:

00h

Description: This register controls both PC Card sockets and is not duplicated for each socket. The host

interrupt mode bits in this register are retained for Intel 82365SL-DF compatibility. See

Table 51 for a complete description of the register contents.

Table 51. ExCA Global-Control Register (Index 1Eh)

BIT

SIGNAL

TYPE

FUNCTION

7-5

RSVD

Reserved. Bits 7-5 are is read only and returns 0s when read. Write transactions have no effect.

INTMODEB

R/W

Level/edge interrupt mode select – card B. Bit 4 selects the signaling mode for the PCI1221 host interrupt

for card B interrupts. This bit is encoded as:

0 = Host interrupt is edge mode (default).

1 = Host interrupt is level mode.

INTMODEA

R/W

Level/edge interrupt mode select – card A. Bit 3 selects the signaling mode for the PCI1221 host interrupt

for card A interrupts. This bit is encoded as:

0 = Host interrupt is edge mode (default).

1 = Host interrupt is level mode.

IFCMODE

R/W

Interrupt flag clear mode select. Bit 2 selects the interrupt flag clear mechanism for the flags in the ExCA

card status change register. This bit is encoded as:

0 = Interrupt flags are cleared by read of CSC register (default).

1 = Interrupt flags are cleared by explicit write back of 1.

CSCMODE

R/W

Card status change level/edge mode select. Bit 1 selects the signaling mode for the PCI1221 host interrupt

for card status changes. This bit is encoded as:

0 = Host interrupt is edge mode (default).

1 = Host interrupt is level mode.

PWRDWN

R/W

Power-down mode select. When bit 0 is set to 1, the PCI1221 is in power-down mode. In power-down

mode, the PCI1221 card outputs are 3-stated until an active cycle is executed on the card interface.

Following an active cycle, the outputs are again 3-stated. The PCI1221 still receives functional interrupts,

and/or card status change interrupts; however, an actual card access is required to wake up the interface.

This bit is encoded as:

0 = Power-down mode is disabled (default).

1 = Power-down mode is enabled.

PCI1221 Datasheet(PDF) 102 Page - Texas Instruments

PCI1221 Datasheet(HTML) 102 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL