PCI1221 datasheet(74/123 Pages) TI

74 / 123 page

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

general-purpose event enable register

Bit

Name

General-purpose event enable

Type

R/W

Default

General-purpose event enable

Type:

Read only, read/write (see individual bit descriptions)

Offset:

AAh (function 0)

Default:

0000h

Description: The general-purpose event enable register contains bits that are set to enable a GPE signal.

The GPE signal is driven until the corresponding status bit is cleared and the event is serviced.

The GPE can only be signaled if one of the multifunction terminals, MFUNC6:0, is configured

for GPE signaling. Access this register only through function 0. See Table 31 for a complete

description of the register contents.

Table 31. General-Purpose Event Enable Register

BIT

SIGNAL

TYPE

FUNCTION

ZV0_EN

R/W

PC card socket 0 ZV enable. When bit 15 is set, a GPE is signaled on a change in status of

ZVENABLE in the function 0 PC Card controller function of the PCI1221.

ZV1_EN

R/W

PC card socket 1 ZV enable. When bit 14 is set, a GPE is signaled on a change in status of

ZVENABLE in the function 1 PC Card controller function of the PCI1221.

13–12

RSVD

Reserved. These bits are read only and return zero when read.

PWR_EN

R/W

Power change enable. When bit 11 is set, a GPE is signaled on when software has changed

the power state of either socket.

10–9

RSVD

Reserved. These bits are read only and return zero when read.

VPP12_EN

R/W

12 Volt VPP request enable. When bit 8 is set, a GPE is signaled when software has changed

the requested VPP level to or from 12 Volts for either card socket.

7–5

RSVD

Reserved. These bits are read only and return zero when read.

GP4_EN

R/W

GPI4 enable. When bit 4 is set, a GPE is signaled when there has been a change in status of

the MFUNC5 terminal input level if configured as GPI4.

GP3_EN

R/W

GPI3 enable. When bit 3 is set, a GPE is signaled when there has been a change in status of

the MFUNC4 terminal input level if configured as GPI3.

GP2_EN

R/W

GPI2 enable. When bit 2 is set, a GPE is signaled when there has been a change in status of

the MFUNC2 terminal input if configured as GPI2.

GP1_EN

R/W

GPI1 enable. When bit 1 is set, a GPE is signaled when there has been a change in status of

the MFUNC1 terminal input if configured as GPI1.

GP0_EN

R/W

GPI0 enable. When bit 0 is set, a GPE is signaled when there has been a change in status of

the MFUNC0 terminal input if configured as GPI0.

PCI1221 Datasheet(PDF) 74 Page - Texas Instruments

PCI1221 Datasheet(HTML) 74 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL