SH7262/SH7264 Group

High-speed Read/Write Serial Flash Memory

Using the Renesas Serial Peripheral Interface

REJ06B0889-0100/Rev.1.00

June 2009

Page 5 of 45

2.3

Interface Timing Example When Accessing in High-speed

This section describes an example of the interface timing when accessing serial flash memory in high-speed. The interface

timing by the typical procedure to control the SPI is explained, as well as the procedure to read/write serial flash memory in

high-speed.

2.3.1

Interface Timing by the Typical Procedure to Control SPI

Figure 2 shows an example of the data transfer timing by the typical procedure to control SPI. According to the

specifications of the serial flash memory used in this application, both master and slave output data on the falling edge of

the clock, and latch data on the rising edge of the clock after a half cycle later. This procedure supports full-duplex

communication.

For details on this procedure, refer to the application note "SH7262/SH7264 Group Interfacing Serial Flash Memory Using

the Renesas Serial Peripheral Interface".

SSL00

RSPCK0

MOSI0

MISO0

: Timing conditions for serial flash memory

: Timing for latching data

bit 0

bit 1

bit 7

Figure 2 Data Transfer Timing Example by the Typical Procedure to Control SPI (CPOL = 1, CPHA =1)