SH7262 datasheet(10/45 Pages) RENESAS

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SH7262/SH7264 Group

High-speed Read/Write Serial Flash Memory

Using the Renesas Serial Peripheral Interface

REJ06B0889-0100/Rev.1.00

June 2009

Page 10 of 45

Table 4 Timing Conditions for Serial Flash Memory When Extending the Setup Time

Symbol

Item

Description

Related registers

tCSLS

Chip Select Low

Setup Time

Time required for the slave to latch data from asserting

SSL to the RSPCK rising.

The following formula must be fulfilled:

tLEAD (=RSPCK delay) + 1/2 x tSPcyc > tCSLS (min)

SPCKD register

SPCMD register

tCSH

Chip Select High

Time

Time required for SSL negation.

The following formula must be fulfilled:

tTD (=2 x Bφ + next access delay) > tCSH (min)

SPND register

SPCMD register

fSCK

Serial Clock

Frequency

The maximum operating frequency supported by the

slave.

The following formula must be fulfilled:

fSCK(max) > 1/ tSPcyc

SPBR register

SPCMD register

tCSLH

Chip select Low

Hold Time

Hold time required from the last RSPCK rising to the SSL

negation.

The following formula must be fulfilled:

tLAG (=SSL negation delay) + 1/2 tSPcyc > tCSLH (min)

SSLND register

SPCMD register

tDS

Data Input Setup

Time

Time required for the master from outputting data to

latching data.

The following formula must be fulfilled:

tSPcyc – tOD(max) > tDS (min)

tDH

Data Input Hold

Time

Time required for the master from latching data to stop

the data output.

The following formula must be fulfilled:

tOH(min) > tDH (min)

Table 5 Timing Conditions for the SH7264 MCU when Extending the Setup Time

Symbol

Item

Description

Related registers

tSU

Data Input Setup

Time

Time required for the slave from outputting data to

latching data.

The following formula must be fulfilled:

tSPcyc – tV (max) > tSU (min)

Data Input Hold

Time

Time required for the slave from latching data to stop the

data output.

The following formula must be fulfilled:

tOH(min) > tH(min)

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