SH7262/SH7264 Group

High-speed Read/Write Serial Flash Memory

Using the Renesas Serial Peripheral Interface

REJ06B0889-0100/Rev.1.00

June 2009

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Extending the Access Width

Specifying the longword-wide access to the Data register (SPDR) reduces the number of times to insert waits (RSPCK

delay, SSL negation delay, the next access delay) before and after the transfer to transfer data effectively.

When issuing the read command (Opcode: H'0B), the number of bytes output by master (command, address, and dummy

data) is five. Therefore, the master outputs and transfers data in byte-wide length, and the slave outputs and transfers data in

longword-wide length. The figure below shows an example of the command sequence of the extended access width.

SSL00

RSPCK0

MOSI0

MISO0

H'0B

addr1

addr2

addr3

dummy

data1

data2

data3

data4

data n

data5

CPOL=1, CPHA=0

Byte-wide access

CPOL = 0, CPHA = 1

Longword-wide access

Figure 8 Command Sequence for Longword-wide Access (Opcode: H'0B)