SH7262/SH7264 Group

High-speed Read/Write Serial Flash Memory

Using the Renesas Serial Peripheral Interface

REJ06B0889-0100/Rev.1.00

June 2009

Page 9 of 45

SSL00

MOSI0

RSPCK0

Set the RSPI as (CPOL=0, CPHA=1)

- Set the RSPCK as 0 when idle

- Latch data on even edge

The master must latch data on the falling edge of the RSPCK to

ensure one cycle after the timing when the slave outputs data.

-> Use the setting (CPOL=1, CPHA = 0) or (CPOL = 0, CPHA = 1).

MISO0

CPOL = 0 setting

changes the RSPCK

polarity.

Slave outputs the first data bit

Slave outputs the

second data bit

Master outputs

the last data bit

Serial flash memory outputs data on the falling edge,

just after commands are input

2

1

RSPCK

frequency

The timing when the master

latches the first data bit

Figure 6 Interface Timing on MISO Transfer (CPOL and CPHA bits are changed)

Figure 7 shows the interface timing when extending the setup time. Table 4 and Table 5 list the timing conditions for serial

flash memory and the SH7264. Set the RSPI to satisfy these conditions.

SSL00

RSPCK0

MOSI0

MISO0

: Timing conditions for serial flash memory

: Timing for latching data

MOSI transfer

MISO transfer

Figure 7 Interface Timing When Extending the Setup Time