IMX35 datasheet(44/148 Pages) FREESCALE

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i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 6

Freescale Semiconductor

WE40A

(muxed

A/D)

CS[x] valid to LBA invalid

WE14 – WE6 + (LBN + LBA + 1

– CSA)

–3 + (LBN + LBA +

1 – CSA)

3 + (LBN + LBA + 1 –

CSA)

WE41

CS[x] valid to Output Data valid

WE16 – WE6 – WCSA

—

3 – WCSA

WE41A

(muxed

A/D)

CS[x] valid to Output Data valid

WE16 – WE6 + (WLBN +

WLBA + ADH + 1 – WCSA)

—

3 + (WLBN + WLBA +

ADH + 1 – WCSA)

WE42

Output Data invalid to CS[x]

Invalid

WE17 – WE7 – CSN

—

3 – CSN

WE43

Input Data valid to CS[x] invalid MAXCO – MAXCSO + MAXDI

MAXCO6 –

MAXCSO7 +

MAXDI8

—ns

WE44

CS[x] invalid to Input Data

invalid

—

WE45

CS[x] valid to BE[y] valid (write

access)

WE12 – WE6 + (WBEA – CSA)

—

3 + (WBEA – CSA)

WE46

BE[y] invalid to CS[x] invalid

(write access)

WE7 – WE13 + (WBEN – CSN)

—

–3 + (WBEN – CSN)

WE47

DTACK valid to CS[x] invalid

MAXCO – MAXCSO + MAXDTI

MAXCO6 –

MAXCSO7 +

MAXDTI9

—ns

WE48

CS[x] Invalid to DTACK invalid

—

1 For the value of parameters WE4–WE21, see column BCD = 0 in Table 30.

2 CS Assertion. This bit field determines when the CS signal is asserted during read/write cycles.

3 CS Negation. This bit field determines when the CS signal is negated during read/write cycles.

4 BE Assertion. This bit field determines when the BE signal is asserted during read cycles.

5 BE Negation. This bit field determines when the BE signal is negated during read cycles.

6 Output maximum delay from internal driving ADDR/control FFs to chip outputs.

7 Output maximum delay from CS[x] internal driving FFs to CS[x] out.

8 DATA maximum delay from chip input data to its internal FF.

DTACK maximum delay from chip dtack input to its internal FF.

Note:

All configuration parameters (CSA, CSN, WBEA, WBEN, LBA, LBN, OEN, OEA, RBEA, and RBEN) are in cycle units.

Table 31. WEIM Asynchronous Timing Parameters Relative Chip Select Table (continued)

Ref No.

Parameter

Determination By

Synchronous Measured

Parameters1

Min

Max

(If 133 MHz is

supported by SoC)

Unit

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