IMX35 datasheet(85/148 Pages) FREESCALE

85 / 148 page

i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 6

Freescale Semiconductor

Figure 62. Asynchronous Parallel System 68k Interface (Type 2) Timing Diagram

Table 54. Asynchronous Parallel Interface Timing Parameters—Access Level

Parameter

Symbol

Min.

Typ.1

Max.

Units

IP27 Read system cycle time

Tcycr

Tdicpr – 1.5

Tdicpr2

Tdicpr + 1.5

IP28 Write system cycle time

Tcycw

Tdicpw – 1.5

Tdicpw3

Tdicpw + 1.5

IP29 Read low pulse width

Trl

Tdicdr – Tdicur – 1.5

Tdicdr4 –Tdicur5 Tdicdr – Tdicur + 1.5

IP30 Read high pulse width

Trh

Tdicpr – Tdicdr +

Tdicur – 1.5

Tdicpr – Tdicdr +

Tdicur

Tdicpr – Tdicdr + Tdicur

+ 1.5

IP31 Write low pulse width

Twl

Tdicdw – Tdicuw

–1.5

Tdicdw6 –

Tdicuw7

Tdicdw – Tdicuw + 1.5

IP32 Write high pulse width

Twh

Tdicpw – Tdicdw +

Tdicuw – 1.5

Tdicpw – Tdicdw

+ Tdicuw

Tdicpw – Tdicdw +

Tdicuw + 1.5

IP33 Controls setup time for read

Tdcsr

Tdicur – 1.5

Tdicur

—

IP34 Controls hold time for read

Tdchr

Tdicpr – Tdicdr – 1.5

Tdicpr – Tdicdr

—

IP28, IP27

Read Data

IP32, IP30

IP37

IP38

DISPB_PAR_RS

DISPB_DATA

DISPB_WR

(Input)

(Output)

IP35,IP33

IP36, IP34

IP31, IP29

IP40

IP39

IP45, IP43

IP42, IP41

DISPB_RD (ENABLE_L)

DISPB_D#_CS

(READ/WRITE)

DISPB_DATA[17]

(ENABLE_H)

read point

IP46,IP44

IP47

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