IMX35 datasheet(46/148 Pages) FREESCALE

Part #	IMX35

Description	i.MX35 Applications Processors for Industrial and Consumer Products

PDF	148 Pages

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Manufacturer	FREESCALE [Freescale Semiconductor, Inc]

Direct Link	http://www.freescale.com

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i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 6

Freescale Semiconductor

NOTE

SDR SDRAM CLK parameters are measured from the 50% point—that is,

high is defined as 50% of signal value and low is defined as 50% of signal

value. SD1 + SD2 does not exceed 7.5 ns for 133 MHz.

The timing parameters are similar to the ones used in SDRAM data

sheets—that is, Table 32 indicates SDRAM requirements. All output signals

are driven by the ESDCTL at the negative edge of SDCLK and the

parameters are measured at maximum memory frequency.

SD7

Address hold time

tAH

1.8

—

SD8

SDRAM access time

tAC

—

6.47

SD9

Data out hold time1

tOH

1.2

—

SD10

Active to read/write command period

tRC

—

clock

1 Timing parameters are relevant only to SDR SDRAM. For the specific DDR SDRAM data related timing parameters, see

Table 40 and Table 41.

Table 32. DDR/SDR SDRAM Read Cycle Timing Parameters (continued)

Parameter

Symbol

Min.

Max.

Unit

IMX35 Datasheet(PDF) 46 Page - Freescale Semiconductor, Inc