IMX35 datasheet(14/148 Pages) FREESCALE

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i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 6

Freescale Semiconductor

4.2

Power Modes

Table 9 provides descriptions of the power modes of the i.MX35 processor.

Table 9. i.MX35 Power Modes

Power

Mode

Description

QVCC (ARM/L2

Peripheral)

MVDD/PVDD

OSC24M_VDD

OSC_AUDO_VDD

Typ.

Max.

Typ.

Max.

Typ.

Max.

Wait

VDD1,2,3,4 = 1.1 V (min.)

ARM is in wait for interrupt mode.

MAX is active.

L2 cache is kept powered.

MCU PLL is on (400 MHz)

PER PLL is off (can be configured)

(default: 300 MHz)

Module clocks are gated off (can be

configured by CGR register).

OSC 24M is ON.

OSC audio is off (can be configured).

RNGC internal osc is off.

—

7.2 mA

—

1.2

—

Doze

VDD1,2,3,4 = 1.1 V (min.)

ARM is in wait for interrupt mode.

MAX is halted.

L2 cache is kept powered.

L2 cache control logic off.

AWB enabled.

MCU PLL is on(400 MHz)

PER PLL is off (can be configured).

(300 Mhz).

Module clocks are gated off (can be

configured by CGR register).

OSC 24M is ON.

OSC audio is off (can be configured)

RNGC internal osc is off

12.4 mA

—

7.2 mA

—

1.2 mA

—

Stop

VDD1,2,3,4 = 1.1 V (min.)

ARM is in wait for interrupt mode.

MAX is halted

L2 cache is kept powered.

L2 cache control logic off.

AWB enabled.

MCU PLL is off.

PER PLL is off.

All clocks are gated off.

OSC 24 MHz is on

OSC audio is off

RNGC internal osc is off

1.1

—

400

µA

—

1.2

—

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