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IMX35 Datasheet(PDF) 77 Page - Freescale Semiconductor, Inc |
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IMX35 Datasheet(HTML) 77 Page - Freescale Semiconductor, Inc |
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77 / 148 page  i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 6 Freescale Semiconductor 77 Additionally, the IPU allows a programmable pause between two bursts. The pause is defined in the HSP_CLK cycles. It allows the prevention of timing violation between two sequential bursts or two accesses to different displays. The range of this pause is from 4 to 19 HSP_CLK cycles. Figure 54. Asynchronous Parallel System 80 Interface (Type 1) Burst Mode Timing Diagram DISPB_D#_CS DISPB_PAR_RS DISPB_WR DISPB_RD DISPB_DATA DISPB_BCLK DISPB_D#_CS DISPB_PAR_RS DISPB_WR DISPB_RD DISPB_DATA DISPB_D#_CS DISPB_PAR_RS DISPB_WR DISPB_RD DISPB_DATA Burst access mode with sampling by CS signal Burst access mode with sampling by separate burst clock (BCLK) Single access mode (all control signals are not active for one display interface clock after each display access) |
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