AT90SCR100 datasheet(88/433 Pages) ATMEL

88 / 433 page

TPR0327AY–SMS–30Jan09

AT90SCR100

Figure 13-1.

8-bit Timer/Counter0 Block Diagram

13.1.1.1

Registers

The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are 8-bit

registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the

Timer Interrupt Flag Register (TIFR0). All interrupts are individually masked with the Timer Inter-

rupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.

The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on

the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter

uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source

is selected. The output from the Clock Select logic is referred to as the timer clock (clkT0).

The double buffered Output Compare Registers (OCR0A and OCR0B) are compared with the

Timer/Counter value at all times. The result of the compare can be used by the Waveform Gen-

erator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and

OC0B). See “Output Compare Unit” on page 90. for details. The Compare Match event will also

set the Compare Flag (OCF0A or OCF0B) which can be used to generate an Output Compare

interrupt request.

13.1.1.2

Definitions

Many register and bit references in this section are written in general form. A A lower case “x”

replaces the Output Compare Unit, in this case Compare Unit A or Compare Unit B. However,

Clock Select

Timer/Counter

OCR0A

OCR0B

TCNT0

Waveform

Generation

Waveform

Generation

OC0A

OC0B

Fixed

TOP

Value

Control Logic

= 0

TOP

BOTTOM

Count

Clear

Direction

TOVn

(Int.Req.)

OC0A

(Int.Req.)

OC0B

(Int.Req.)

TCCR0A

TCCR0B

Edge

Detector

( From Prescaler )

clk

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