AT90SCR100 datasheet(98/433 Pages) ATMEL

98 / 433 page

TPR0327AY–SMS–30Jan09

AT90SCR100

Figure 13-10.

Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (fclk_I/O/8)

Figure 13-11 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast

PWM mode where OCR0A is TOP.

Figure 13-11.

Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-

caler (fclk_I/O/8)

13.1.9

8-bit Timer/Counter0 Register Description

13.1.9.1

TCCR0A – Timer/Counter Control Register A

• Bits 7..6 – COM0A1..0: Compare Match Output A Mode

These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0

bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is con-

nected. However, note that the Data Direction Register (DDR) bit corresponding to which the

OC0A pin must be set in order to enable the output driver.

OCF0x

OCR0x

TCNT0

OCR0x Value

OCR0x - 1

OCR0x

OCR0x + 1

OCR0x + 2

clk

I/O

clk

(clk

I/O /8)

OCF0x

OCR0x

TCNT0

(CTC)

TOP

TOP - 1

TOP

BOTTOM

BOTTOM + 1

clk

I/O

clk

(clk

I/O /8)

Bit

7654

0x24 (0x44)

COM0A1 COM0A0 COM0B1 COM0B0

WGM01

WGM00

TCCR0A

Read/write

R/W

Initial value

0000

0x00

AT90SCR100 Datasheet(PDF) 98 Page - ATMEL Corporation

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