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AT90SCR100 Datasheet(PDF) 24 Page - ATMEL Corporation |
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AT90SCR100 Datasheet(HTML) 24 Page - ATMEL Corporation |
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24 / 433 page  24 TPR0327AY–SMS–30Jan09 AT90SCR100 In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. 6.3.2 EEARH and EEARL – The EEPROM Address Register • Bits 15..12 – Res : Reserved Bits These bits are reserved bits in the AT90SCR100 and will always read as zero. • Bits 11..0 – EEAR8..0 : EEPROM Address The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 4K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4096. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. 6.3.3 EEDR – The EEPROM Data Register • Bits 7..0 – EEDR7..0 : EEPROM Data For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address specified by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address specified by EEAR. 6.3.4 EECR – The EEPROM Control Register • Bits 7..6 – Res: Reserved Bits These bits are reserved bits in the AT90SCR100 and will always read as zero. Bit 15 141312 11 10 9 8 0x22 (0x42) ---- EEAR [11..8] EEARH 0x21 (0x41) EEAR [7..0] EEARL Bit 7 6543 2 1 0 Read/write RRRR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 x x x x xxxxx x x x Bit 7654 3 2 1 0 0x20 (0x40) EEDR [7..0] EEDR Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0000 0 0 0 0 0x00 Bit 7654 3 2 1 0 0x1F (0x3F) - - EEPM1 EEPM0 EERIE EEMPE EEPE EERE EECR Read/write R R R/W R/W R/W R/W R/W R/W Initial value 0 0 x x 0 0 x 0 |
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