AT90SCR100 datasheet(40/433 Pages) ATMEL

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TPR0327AY–SMS–30Jan09

AT90SCR100

7.3

Clock Output Buffer

The device can output the system clock clkCORE on the CLKO pin. To enable the output, the

CKOUT Fuse has to be programmed. This mode is suitable when the chip clock is used to drive

other circuits on the system. The clock will also be output during reset, and the normal operation

of the I/O pin will be overriden when the fuse is programmed.

7.4

Clock System Registers

7.4.1

PLLCR – Phase Lock Loop (PLL) Control Register

• Bit 7 – PLLMUX : PLL Clock Multiplexer Control bit

Set this bit (1) to switch Clock Multiplexer (clkMUX) to PLL clock (clkPLL).

Clear this bit (0) to switch clkMUX to external clock (clkXTAL).

• Bit 6..2 – Reserved Bits

These bits are reserved for future use.

• Bit 1 – LOCK : PLL Lock Bit Signal

This bit is set by hardware as soon as the clock generated by the PLL (clkPLL) is stable. It is for-

bidden to switch clkMUX to clkPLL if the LOCK bit is not set.

Wait for the PLLCR.LOCK bit to be set before switching to clkPLL using the PLLMUX bit.

• Bit 0 – ON : PLL Start Bit

Setting this bit (1) will start the PLL. As soon as LOCK bit is set, you can switch on clkPLL clock,

not before.

Clearing this bit (0) will stop the PLL.

7.4.2

CLKPR – Clock Prescale Register

• Bit 7..4 – Reserved Bits

These bits are reserved for future use.

Bit

7654

$000062

PLLMUX

----

LOCK

PLLCR

Read/write

R/W

RRRR

R/W

Initial value

0000

0x00

When the CPU runs on clkPLL, and the PLL is stopped, the CPU will be clcked no

longer. This will freeze the CPU and only a reset will be able to start the CPU

again.

Before stopping the PLL, make sure that the CPU uses External Clock clkXTAL by

using the PLLMUX register.

Caution

Bit

7654

$000061

----

CLKPS3

CLKPS2

CLKPS1 CLKPS0

CLKPR

Read/write

RRRR

R/W

Initial value

0000

0x00

AT90SCR100 Datasheet(PDF) 40 Page - ATMEL Corporation

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