PIC16F1933-ESLASHP datasheet(54/418 Pages) MICROCHIP

54 / 418 page

PIC16F193X/LF193X

DS41364A-page 52

Preliminary

2.3

PCL and PCLATH

The Program Counter (PC) is 15 bits wide. The low byte

comes from the PCL register, which is a readable and

writable register. The high byte (PC<14:8>) is not directly

readable or writable and comes from PCLATH. On any

Reset, the PC is cleared. Figure 2-4 shows the five

situations for the loading of the PC.

FIGURE 2-4:

LOADING OF PC IN

DIFFERENT SITUATIONS

2.3.1

MODIFYING PCL

Executing any instruction with the PCL register as the

destination simultaneously causes the Program Coun-

ter PC<14:8> bits (PCH) to be replaced by the contents

of the PCLATH register. This allows the entire contents

of the program counter to be changed by writing the

desired upper 7 bits to the PCLATH register. When the

lower 8 bits are written to the PCL register, all 15 bits of

the program counter will change to the values con-

tained in the PCLATH register and those being written

to the PCL register.

2.3.2

COMPUTED GOTO

A computed GOTO is accomplished by adding an offset to

the program counter (ADDWF PCL). When performing a

table read using a computed GOTO method, care should

be exercised if the table location crosses a PCL memory

boundary (each 256-byte block). Refer to the Application

Note AN556, “Implementing a Table Read” (DS00556).

2.3.3

COMPUTED FUNCTION CALLS

A computed function CALL allows programs to maintain

tables of functions and provide another way to execute

state machines or look-up tables. When performing a

table read using a computed function CALL, care

should be exercised if the table location crosses a PCL

memory boundary (each 256-byte block).

If using the CALL instruction, the PCH<2:0> and PCL

registers are loaded with the operand of the CALL

instruction. PCH<6:3> is loaded with PCLATH<6:3>.

The CALLW instruction enables computed calls by com-

bining PCLATH and W to form the destination address.

A computed CALLW is accomplished by loading the W

The PCL register is loaded with the value of W and

PCH is loaded with PCLATH.

2.3.4

BRANCHING

The branching instructions add an offset to the PC.

This allows relocatable code and code that crosses

page boundaries. There are two forms of branching,

BRW

and BRA. The PC will have incremented to fetch

the next instruction in both cases. When using either

branching instruction, a PCL memory boundary may be

crossed.

If using BRW, load the W register with the desired

unsigned address and execute BRW. The entire PC will

be loaded with the address PC + 1 + W.

If using BRA, the entire PC will be loaded with PC + 1 +,

the signed value of the operand of the BRA instruction.

2.4

Stack

All devices have a 16-level x 15-bit wide hardware

stack (refer to Figures 2-1 and 2-3). The stack space is

not part of either program or data space. The PC is

PUSHed onto the stack when CALL or CALLW instruc-

tions are executed or an interrupt causes a branch. The

stack is POPed in the event of a RETURN, RETLW or a

RETFIE

instruction execution. PCLATH is not affected

by a PUSH or POP operation.

The stack operates as a circular buffer, if the STVREN

bit = 0 (Configuration Word 2). This means that after

the stack has been PUSHed sixteen times, the seven-

teenth PUSH overwrites the value that was stored from

the first PUSH. The eighteenth PUSH overwrites the

second PUSH (and so on).

PCL

PCH

ALU Result

PCLATH

PCL

PCH

6 4

OPCODE <10:0>

PCLATH

PCL

PCH

PCLATH

Instruction with

PCL as

Destination

GOTO, CALL

CALLW

PCL

PCH

PC + W

BRW

PCL

PCH

PC + OPCODE <8:0>

BRA

Note 1: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of the

CALL,

CALLW

RETURN

RETLW

and

RETFIE

instructions or the vectoring to

an interrupt address.

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