PIC16F1933-ESLASHP datasheet(74/418 Pages) MICROCHIP

74 / 418 page

PIC16F193X/LF193X

DS41364A-page 72

Preliminary

4.3

Interrupts During Sleep

Some interrupts can be used to wake from Sleep. To

wake from Sleep, the peripheral must be able to

operate without the system clock. The interrupt source

must have the appropriate Interrupt Enable bit(s) set

prior to entering Sleep.

On waking from Sleep, if the GIE bit is also set, the

processor will branch to the interrupt vector. Otherwise,

the processor will continue executing instructions after

the SLEEP instruction. The instruction directly after the

SLEEP

instruction will always be executed before

branching to the ISR. Refer to the Section 24.0

“Power-Down Mode (Sleep)” for more details.

4.4

INT Pin

The

external

interrupt,

INT

pin,

causes

asynchronous, edge-triggered interrupt. The INTEDG bit

of the OPTION register determines on which edge the

interrupt will occur. When the INTEDG bit is set, the

rising edge will cause the interrupt. When the INTEDG

bit is clear, the falling edge will cause the interrupt. The

INTF bit of the INTCON register will be set when a valid

edge appears on the INT pin. If the GIE and INTE bits

are also set, the processor will redirect program

execution to the interrupt vector. This interrupt is

disabled by clearing the INTE bit of the INTCON register.

4.5

Context Saving

Upon entering an interrupt, the return PC address is

saved on the stack. Additionally, the following registers

are automatically saved in the shadow registers:

• W register

• STATUS register (except for TO and PD)

• BSR register

• FSR registers

• PCLATH register

Upon exit from the Interrupt Service Routine, these reg-

isters are automatically restored. Any modifications to

these registers during the ISR will be lost. Depending

on the user’s application, other registers may also need

to be saved.

PIC16F1933-E/P Datasheet(PDF) 74 Page - Microchip Technology

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