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PIC16F1933-E/P Datasheet(PDF) 94 Page - Microchip Technology

Part # PIC16F1933-E/P
Description  28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology
PDF  418 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC16F1933-E/P Datasheet(HTML) 94 Page - Microchip Technology

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PIC16F193X/LF193X
DS41364A-page 92
Preliminary
© 2008 Microchip Technology Inc.
6.3.4
PORTB FUNCTIONS AND OUTPUT
PRIORITIES
Each PORTB pin is multiplexed with other functions. The
pins, their combined functions and their output priorities
are briefly described here. For additional information,
refer to the appropriate section in this data sheet.
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the lowest number in
the following lists.
RB0
1.
SEG0 (LCD)
2.
CCP4, 28-pin only
3.
RB0
RB1
1.
P1C (ECCP1), 28-pin only
2.
RB1
RB2
1.
P1B (ECCP1), 28-pin only
2.
RB2
RB3
1.
CCP2/P2A
2.
RB3
RB4
1.
COM0
2.
P1D, 28-pin only
3.
RB4
RB5
1.
COM1
2.
P2B, 28-pin only
3.
P3A
4.
RB5
RB6
1.
ICSPCLK (Programming)
2.
ICDCLK (enabled by Configuration Word)
3.
SEG14 (LCD)
4.
RB6
RB7
1.
ICSPDAT (Programming)
2.
ICDDAT (enabled by Configuration Word)
3.
SEG13 (LCD)
4.
RB7
TABLE 6-2:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ADCON0
—
CHS4
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
137
ANSELB
—
—
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
91
APFCON
—CCP3SEL
T1GSEL
P2BSEL
SRNQSEL
C2OUTSEL
SSSEL
CCP2SEL
84
CCPxCON
PxM1
PxM0
DCxB1
DCxB0
CCPxM3
CCPxM2
CCPxM1
CCPxM0
184
CPSCON0
CPSON
—
—
—
CPSRNG1
CPSRNG0
CPSOUT
T0XCS
180
CPSCON1
—
—
—
—
CPSCH3
CPSCH2
CPSCH1
CPSCH0
181
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
73
IOCBP
IOCBP7
IOCBP6
IOCBP5
IOCBP4
IOCBP3
IOCBP2
IOCBP1
IOCBP0
104
IOCBN
IOCBN7
IOCBN6
IOCBN5
IOCBN4
IOCBN3
IOCBN2
IOCBN1
IOCBN0
104
IOCBF
IOCBF7
IOCBF6
IOCBF5
IOCBF4
IOCBF3
IOCBF2
IOCBF1
IOCBF0
104
LATB
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
90
LCDCON
LCDEN
SLPEN
WERR
—
CS1
CS0
LMUX1
LMUX0
243
LCDSE0
SE7
SE6
SE5
SE4
SE3
SE2
SE1
SE0
247
LCDSE1
SE15
SE14
SE13
SE12
SE11
SE10
SE9
SE8
247
OPTION_REG
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
PS2
PS1
PS0
51
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
90
T1GCON
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/DONE
T1GVAL
T1GSS1
T1GSS0
170
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
91
WPUB
WPUB7
WPUB6
WPUB5
WPUB4
WPUB3
WPUB2
WPUB1
WPUB0
90
Legend:
x
= unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTB.



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