PIC16F1933-ESLASHP datasheet(71/418 Pages) MICROCHIP

71 / 418 page

Preliminary

DS41364A-page 69

PIC16F193X/LF193X

4.0

INTERRUPTS

The PIC16F193X/LF193X device family features an

interruptible core, allowing certain events to preempt

normal program flow. An Interrupt Service Routine

(ISR) is used to determine the source of the interrupt

and act accordingly. Some interrupts can be configured

to wake the MCU from Sleep mode.

The PIC16F193X/LF193X device family has 23 inter-

rupt sources, differentiated by corresponding interrupt

enable and flag bits:

• External Edge Detect on INT Pin Interrupt

• Interrupt-on-Change Interrupt

• A/D Conversion Complete Interrupt

• EEPROM Write Complete Interrupt

• EUSART Receive Interrupt

• EUSART Transmit Interrupt

• LCD Module Interrupt

• Oscillator Fail Interrupt

• Timer0 Overflow Interrupt

• Timer1 Gate Interrupt

• Timer1 Overflow Interrupt

• Timer2 Match with PR2 Interrupt

• Timer4 Match with PR4 Interrupt

• Timer6 Match with PR6 Interrupt

• Comparator C1 Interrupt

• Comparator C2 Interrupt

• CCP1 Event Interrupt

• CCP2 Event Interrupt

• CCP3 Event Interrupt

• CCP4 Event Interrupt

• CCP5 Event Interrupt

• MSSP Event Interrupt

• MSSP Bus Collision Interrupt

A block diagram of the interrupt logic is shown in

Figure 4-1.

FIGURE 4-1:

INTERRUPT LOGIC

TMR0IF

TMR0IE

INTF

INTE

IOCIF

IOCIE

GIE

PEIE

Wake-up (If in Sleep mode)

Interrupt to CPU

From Peripheral Interrupt

Logic (Figure 4-2)

PIC16F1933-E/P Datasheet(PDF) 71 Page - Microchip Technology

PIC16F1933-E/P Datasheet(HTML) 71 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL