ADS8331IBRGET datasheet(28/43 Pages) TI

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ADS8331

ADS8332

SBAS363 – DECEMBER 2009

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WRITING TO THE CONVERTER

There are two different types of writes to the register: a 4-bit write to the CMR and a full 16-bit write to the CMR

plus CFR. The command set is listed in Table 4 and the configuration register map is listed in Table 5. A simple

command requires only four SCLKs; the write takes effect on the fourth falling edge of SCLK. A 16-bit write or

read takes at least 16 SCLKs (see Table 7 for exceptions that require more than 16 SCLKs).

Configuring the Converter and Default Mode

The converter can be configured with command 1110b (write to the CFR) or command 1111b (default mode). A

write to the CFR requires a 4-bit command followed by 12 bits of data. A 4-bit command takes effect on the

fourth falling edge of SCLK. A write to the CFR takes effect on the 16th falling edge of SCLK.

The CFR default value for each bit is '1'. The default values are applied to the CFR after issuing command 1111b

or when the device is reset with a power-on reset (POR), software reset, or external reset using the RESET pin

(see the Reset Function section).

READING THE CONFIGURATION REGISTER

The host processor can read back the value programmed in the CFR by issuing command 1100b. The timing is

similar to reading a conversion result except CONVST is not used. There is also no activity on the EOC/INT pin.

The CFR value readback contains the first four bits (MSBs) of the previous conversion data plus the 12-bit CFR

contents.

Table 5. Configuration Register (CFR) Map

CFR SDI BIT

(Default = FFFh)

DEFINITION

BIT = '0'

BIT = '1'

Channel select mode

Manual channel select enabled. Use channel

Auto channel select enabled. Channels are

D11

select commands to access a desired

sampled and converted sequentially until the

channel.

cycle after this bit is set to 0.

D10

Conversion clock (CCLK) source select

Conversion clock (CCLK) = SCLK/2

Conversion clock (CCLK) = internal OSC

Trigger (conversion start) select: start

Auto-Trigger: conversions automatically start

conversion at the end of sampling (EOS). If

Manual-Trigger: conversions manually start

three conversion clocks after EOC at

D9 = '0' and D8 = '0', the D4 setting is

on falling edge of CONVST

500kSPS

ignored.

Sample rate for Auto-Trigger mode

500kSPS (21 CCLKs)

250kSPS (42 CCLKs)

Pin 10 polarity select when used as an

EOC/INT active high

EOC/INT active low

output (EOC/INT)

Pin 10 function select when used as an

Pin used as INT

Pin used as EOC

output (EOC/INT)

Pin 10 I/O select for daisy-chain mode

Pin 10 is used as CDI input

Pin 10 is used as EOC/INT output

operation

(daisy-chain mode enabled)

Auto-Nap Power-Down enable/disable.

Auto-Nap Power-Down mode enabled (not

This bit setting is ignored if D9 = '0' and D8

Auto-Nap Power-Down mode disabled

activated)

='0'.

Nap Power-Down. This bit is set to 1

Nap Power-Down disabled

Nap Power-Down enabled

automatically by wake-up command.

(resume normal operation)

Deep Power-Down. This bit is set to 1

Deep Power-Down disabled

Deep Power-Down enabled

automatically by wake-up command.

(resume normal operation)

TAG bit output enabled. TAG bits appear

TAG bit output enable

TAG bit output disabled

after conversion data

Software reset

System reset, returns to '1' automatically

Normal operation

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