ADS8331IBRGET datasheet(20/43 Pages) TI

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Oscillator

Divideby2

ConversionClock

(CCLK)

CFR_D10

SPISerial

Clock(SCLK)

SCLK

Muxswitch

<30ns

NEW

OLD

ADS8331

ADS8332

SBAS363 – DECEMBER 2009

www.ti.com

REFERENCE

The ADS8331/32 can operate with an external reference with a range from 1.2V to 4.2V. A clean, low-noise

reference voltage on this pin is required to ensure good converter performance. A low-noise band-gap reference

such as the REF5025 or REF5040 can be used to drive this pin. A 10

μF ceramic bypass capacitor is required

between the REF+ and REF– pins of the converter. This capacitor should be placed as close as possible to the

pins of the device. Note that the REF– pin should not be connected to the AGND pin of the converter; instead,

the REF– pin must be connected to the analog ground plane with a separate via.

CONVERTER OPERATION

The ADS8331/32 has an internal oscillator that can be used as the conversion clock (CCLK) source. The

minimum frequency of this oscillator is 10.5MHz. The internal oscillator is only active during the conversion

period unless the converter is using Auto-Trigger and/or Auto-Nap modes. The minimum acquisition/sampling

time for the ADS8331/32 is 3 CCLKs (250ns with a 12MHz conversion clock), while the minimum conversion time

is 18 CCLKs (1500ns with a 12MHz conversion clock).

As shown in Figure 37, the ADS8331/32 can also be programmed to run conversions using the external serial

clock (SCLK). This feature allows system designers to achieve system synchronization. Each rising edge of

SCLK toggles the state of the conversion clock (CCLK), which reduces the frequency of SCLK by a factor of two

before it is used as CCLK. For example, a 21MHz SCLK provides a 10.5MHz CCLK. If the start of a conversion

must occur on a specific rising edge of SCLK when the external serial clock is used for the conversion clock (and

Manual-Trigger mode is enabled), a minimum setup time of 20ns between the falling edge of CONVST and the

rising edge of SCLK must be met. This timing ensures the conversion is completed in 18 CCLKs (36 SCLKs).

The duty cycle of SCLK is not critical, as long as the minimum high and low times (11ns for VA = 5.0V) are

satisfied. Because the ADS8331/32 is designed for high-speed applications, a high-frequency serial clock must

be supplied to maintain the high throughput of the interface. This requirement can be accomplished if the period

of SCLK is at most 1

μs when SCLK is used as the conversion clock (CCLK). The 1μs maximum period for SCLK

is also set by the leakage of charge from the capacitors in the capacitive digital-to-analog converter (CDAC)

block in the ADS8331/32. If SCLK is used as the conversion clock, the SCLK source must have minimal rise/fall

times and low jitter to provide the best converter performance.

Figure 37. Conversion Clock Source

Manual Channel Select Mode

Manual Channel Select mode is enabled through the Configuration register (CFR) by setting the CFR_D11 bit to

'0' (see Table 5). The acquisition process starts with selecting an input channel. This selection is done by writing

the desired channel number to the Command register (CMR); see Table 4 for further details. The associated

timing diagram is shown in Figure 38.

Figure 38. Manual Channel Select Timing

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