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ADS8331IBRGET Datasheet(PDF) 32 Page - Texas Instruments

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Part # ADS8331IBRGET
Description  Low-Power, 16-Bit, 500kSPS, 4-/8-Channel Unipolar Input ANALOG-TO-DIGITAL CONVERTERS with Serial Interface
PDF  43 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

ADS8331IBRGET Datasheet(HTML) 32 Page - Texas Instruments

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CONVST
CONVST
#1
#3
EOC#1
(activelow)
CS #2
#3
CS
SCLK#1
SCLK#2
SCLK#3
SDO#1
CDI#2
SDO#2
CDI#3
Conversion N
Conversion(
fromDevice#2
N
1)
-
(1)
1..............16
ManualTrigger,ReadWhileSampling
(UseinternalCCLK,EOCactivelow,andTAGmodedisabled)
High-Z
High-Z
High-Z
CS #1
t
=18CCLK
CONV
t
=3CCLKmin
SAMPLE1
t
SU2
t
SU2
High-Z
SDO#3
High-Z
High-Z
1..............16
1..............16
Conversion
fromDevice#3
N
Conversion
fromDevice#1
N
Conversion
fromDevice#1
N
Conversion
fromDevice#2
(N
1)
-
(1)
Conversion
fromDevice#1
N
SDI#1
SDI#2
SDI#3
Don'tCare
Configure
ReadData
ReadData
Don'tCare
CONVST #2
ADS8331
ADS8332
SBAS363 – DECEMBER 2009
www.ti.com
Figure 49 shows a slightly different scenario where CONVST is not shared with the second converter. Converters
#1 and #3 have the same CONVST signal. In this case, converter #2 simply passes previous conversion data
downstream.
(1)
Data from device #2 is from previous converison.
Figure 49. Simplified Daisy-Chain Mode Timing with Separate CONVST and Continuous CS
The number of SCLKs required for a serial read cycle depends on the combination of different read modes, TAG
mode, daisy-chain mode, and the manner in which a channel is selected (for example, Auto Channel Select
mode). The required number of SCLKs for different readout modes are listed in Table 7.
Table 7. Required SCLKs For Different Readout Mode Combinations
DAISY-CHAIN MODE
TAG MODE
NUMBER OF SCLK CYCLES
CFR_D5
CFR_D1
PER SPI READ
TRAILING BITS
1
0
16
None
1
1
≥ 19
TAG bits plus up to 5 zeros
0
0
16
None
0
1
24
TAG bits plus 5 zeros
32
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Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS8331 ADS8332



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