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ADS8331IBRGET Datasheet(PDF) 30 Page - Texas Instruments |
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ADS8331IBRGET Datasheet(HTML) 30 Page - Texas Instruments |
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30 / 43 page ![]() ADS8331/32 #1 SDI SDO SDI SDO SDI SDO MICROCONTROLLER SDI SDO CS1 CS2 CS3 ProgramDevice#1:CFR_D5= ‘1’ INT CS CONVST CS CONVST CS CONVST EOC/INT CDI CDI ProgramDevices#2and#3:CFR_D5= ‘0’ SCLK SCLK SCLK SCLK ADS8331/32 #2 ADS8331/32 #3 CONVST CONVST CONVST #1 #2 #3 EOC#1 (activelow) CS #2 #3 CS SCLK#1 SCLK#2 SCLK#3 SDO#1 CDI#2 SDO#2 CDI#3 Conversion N Conversion fromDevice#2 N 1..............16 ManualTrigger,ReadWhileSampling (UseinternalCCLK,EOCactivelow,andTAGmodedisabled) High-Z High-Z High-Z CS #1 t =18CCLK CONV t =3CCLKmin SAMPLE1 t SU2 t SU2 High-Z SDO#3 High-Z High-Z 1..............16 1..............16 Conversion fromDevice#3 N Conversion fromDevice#1 N Conversion fromDevice#1 N Conversion fromDevice#2 N Conversion fromDevice#1 N SDI#1 SDI#2 SDI#3 Don'tCare Configure ReadData ReadData Don'tCare ADS8331 ADS8332 SBAS363 – DECEMBER 2009 www.ti.com Figure 46. Multiple Converters Connected Using Daisy-Chain Mode When multiple converters are used in daisy-chain mode, the first converter is configured in regular mode while the rest of the converters downstream are configured in daisy-chain mode. When a converter is configured in daisy-chain mode, the CDI input data go straight to the output register. Therefore, the serial input data passes through the converter with either a 16 SCLK (if the TAG feature is disabled) or 24 SCLK delay, as long as CS is active. See Figure 47 for detailed timing. In this timing diagram, the conversion in each converter is performed simultaneously. Figure 47. Simplified Dasiy-Chain Mode Timing with Shared CONVST and Continuous CS 30 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ADS8331 ADS8332 |
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