Logic

Delay

<=8.3ns

ADS8331/32#3

Q

D

CLK

Logic

Delay

<= . ns

Q

D

CLK

Logic

Delay

<=8.3ns

Q

D

CLK

SCLKinput

SDO

SDO

SDO

CDI

CDI

CDI

Serialdata

input

Serialdata

output

Logic

Delay

PlusPAD

2.7ns

Logic

Delay

PlusPAD

2.7ns

Logic

Delay

PlusPAD

8.3ns

Logic

Delay

PlusPAD

8.3ns

Logic

Delay

PlusPAD

2.7ns

Logic

Delay

PlusPAD

8.3ns

ADS8331/32#2

ADS8331/32#1

ADS8331

ADS8332

www.ti.com

SBAS363 – DECEMBER 2009

SCLK skew between converters and data path delay through the converters configured in daisy-chain mode can

affect the maximum frequency of SCLK. The delay can also be affected by supply voltage and loading. It may be

necessary to slow down the SCLK when the devices are configured in daisy-chain mode. Typical delays are

shown in Figure 50.

Figure 50. Typical Delays Through Converters Configured in Daisy-Chain Mode

RESET FUNCTION

The ADS8331/32 can be reset with three different methods: internal POR, software reset, and external reset

using the RESET pin.

The internal POR circuit is activated when power is initially applied to the converter. This internal circuit

eliminates the need for commands to be sent to the converter after power-on in order to set the default mode of

operation (see the Power-On Sequence Timing section for further details).

Software reset can be used to place the converter in the default mode by setting the CFR_D0 bit to '0' in the

Configuration register (see Table 5). This bit is automatically returned to '1' (default) after the converter is reset.

This reset method is useful in systems that cannot dedicate a separate control signal to the RESET pin. In these

situations, the RESET pin must be connected to VBD in order for the ADS8331/32 to operate properly.

If communication in the system becomes corrupted and a software reset cannot be issued, the RESET pin can

be used to reset the device manually. In order to reset the device and return the device to default mode, this pin

must held low for a minimum of 25ns.

After the ADS8331/32 detects a reset condition, the minimum time before the device can be reconfigured by

FS/CS going low and data clocking in on SDI is 2

μs.

Copyright © 2009, Texas Instruments Incorporated

Submit Documentation Feedback

33

Product Folder Link(s): ADS8331 ADS8332