ADS8331IBRGET datasheet(23/43 Pages) TI

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CCLK

CONVST

CONVST_OUT

(internal)

NAP_ACTIVE

(internal)

EOC

(activelow)

1Cycle

3+3=6Cycles

ADS8331

ADS8332

www.ti.com

SBAS363 – DECEMBER 2009

Power-Down Modes and Acquisition Time

There are three power-down modes that reduce power dissipation: Nap, Deep, and Auto-Nap. The first two, Nap

and Deep Power-Down modes, are enabled/disabled by bits CFR_D3 and CFR_D2, respectively, in the

Configuration register (see Table 5 for details).

Deep Power-Down mode provides maximum power savings. When this mode is enabled, the analog core in the

converter is shut down, and the analog supply current falls from 6.6mA (VA = 5.0V) to 1

μA in 2μs. The wakeup

time from Deep Power-Down mode is 1

μs. The device can wake up from Deep Power-Down mode by either

disabling this mode, issuing the wakeup command, loading the default value into the CFR, or performing a reset

(either with the software reset command, CFR_D0 bit, or the external reset). See Table 4 and Table 5 along with

the Reset Function section for further information.

In Nap Power-Down mode, the bias currents for the analog core of the device are significantly reduced. Because

the bias currents are not completely shut off, the ADS8331/32 can wake up from this power-down mode much

faster than from Deep Power-Down mode. After Nap Power-Down mode is enabled, the analog supply current

falls from 6.6mA (VA = 5.0V) to 0.39mA in 200ns. The wakeup time from this mode is three conversion clock

cycles (CCLK). The device can wake up from Nap Power-Down mode in the same manner as waking up from

Deep Power-Down mode.

The third power-down mode, Auto-Nap, is enabled/disabled by bit CFR_D4 in the Configuration register (see

Table 5 for details). Once this mode is enabled, the device is controlled by the digital core logic on the chip. The

device is automatically placed into Nap Power-Down mode after the next end of conversion (EOC). The analog

supply current falls from 6.6mA (VA = 5.0V) to 0.39mA in 200ns. A conversion start wakes up the device in three

conversion clock cycles. Issuing the wake-up command, loading the default value into the CFR, disabling

Auto-Nap Power-Down mode, issuing a manual channel select command, or resetting the device can wake the

ADS8331/32 from Auto-Nap Power-Down mode. A comparison of the three power-down modes is listed in

Table 2.

Table 2. Comparison of Power-Down Modes

POWER

TYPE OF

CONSUMPTION

POWER-DOWN

(VA = 5.0V)

BY:

POWER-DOWN TIME

WAKEUP BY:

WAKEUP TIME

ENABLE

Normal operation

6.6mA

—

Deep power-down

μA

Setting CFR_D2

μs

Wakeup command 1011b

μs

Set CFR_D2

Nap power-down

0.39mA

Setting CFR_D3

200ns

Wakeup command 1011b

3 CCLKs

Set CFR_D3

Auto-Nap

EOC (end of

CONVST, any channel select command, default

0.39mA

200ns

3 CCLKs

Set CFR_D4

power-down

conversion)

command 1111b, or wakeup command 1011b.

The default acquisition time is three conversion clock (CCLK) cycles. Figure 41 shows the timing diagram for

CONVST, EOC, and auto-nap power-down signals in Manual-Trigger mode. As shown in the diagram, the device

wakes up after a conversion is triggered by the CONVST pin going low. However, a conversion is not yet started

at this time. The conversion start signal to the analog core of the chip is internally generated no less than six

conversion clock (CCLK) cycles later, to allow at least three CCLKs for wake up and three CCLKs for acquisition.

The ADS8331/32 enters Nap Power-Down mode one conversion cycle after the end of conversion (EOC).

Figure 41. Timing for CONVST, EOC, and Auto-Nap Power-Down Signals in Manual-Trigger Mode (Three

Conversion Clock Cycles for Acquisition)

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