PCF8576 datasheet(29/44 Pages) PHILIPS

29 / 44 page

2001 Oct 02

Philips Semiconductors

Product speciﬁcation

Universal LCD driver for low multiplex rates

PCF8576

11 AC CHARACTERISTICS

VDD = 2 to 9 V; VSS =0V; VLCD =VDD − 2VtoVDD − 9 V; Tamb = −40 to +85 °C; unless otherwise speciﬁed.

Notes

1. At fclk < 125 kHz, I2C-bus maximum transmission speed is derated.

2. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to

VIL and VIH with an input voltage swing of VSS to VDD.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

fclk

oscillator frequency on pin CLK

normal mode

VDD = 5 V; note 1

125

200

288

kHz

power-saving mode

VDD = 3.5 V

kHz

tclkH

CLK HIGH time

see Fig.21

−−µs

tclkL

CLK LOW time

−−µs

tPSYNC

SYNC propagation delay time

−−

400

tSYNCL

SYNC LOW time

−−µs

tPLCD

driver delays with test loads

VLCD =VDD − 5 V; see Fig.20 −−

µs

Timing characteristics: I2C-bus; note 2; see Fig.22

tSW

tolerable spike width on bus

−−

100

tBUF

bus free time

4.7

−−µs

tHD;STA

START condition hold time

4.0

−−µs

tSU;STA

set-up time for a repeated START condition

4.7

−−µs

tLOW

SCL LOW time

4.7

−−µs

tHIGH

SCL HIGH time

4.0

−−µs

SCL and SDA rise time

−−

µs

SCL and SDA fall time

−−

0.3

µs

capacitive bus line load

−−

400

tSU;DAT

data set-up time

250

−−

tHD;DAT

data hold time

−−

tSU;STO

set-up time for STOP condition

4.0

−−µs

Fig.20 Test loads.

MBE544

Ω

3.3 k

Ω

1.5 k

0.5VDD

VDD

SDA,

SCL

CLK

1 nF

BP0 to BP3, and

S0 to S39

(2%)

Ω

6.8

VDD

SYNC

(2%)

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