MSP430F4152IPM datasheet(49/82 Pages) TI

49 / 82 page

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

POST OFFICE BOX 655303

 DALLAS, TEXAS 75265

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

flash memory

PARAMETER

TEST

CONDITIONS

VCC

MIN

NOM

MAX

UNIT

VCC(PGM/

ERASE)

Program and Erase supply voltage

2.2

3.6

fFTG

Flash Timing Generator frequency

257

476

kHz

IPGM

Supply current from DVCC during program

2.5V/3.6V

IERASE

Supply current from DVCC during erase

2.5V/3.6V

tCPT

Cumulative program time

seeNote1

2.5V/3.6V

tCMErase

Cumulative mass erase time

seeNote2

2.5V/3.6V

200

Program/Erase endurance

104

105

cycles

tRetention

Data retention duration

TJ =25C

100

years

tWord

Word or byte program time

tBlock, 0

Block program time for 1st byte or word

tBlock, 1-63

Block program time for each additional byte or word

see Note 3

tBlock, End

Block program end-sequence wait time

seeNote3

tFTG

tMass Erase

Mass erase time

5297

tSeg Erase

Segment erase time

4819

NOTES: 1. The cumulative program time must not be exceeded when writing to a 64--byte flash block. This parameter applies to all programming

methods: individual word/byte write and block write modes.

2. The mass erase duration generated by the flash timing generator is at least 11.1 ms ( = 5297x1 / fFTG, max = 5297 x 1 / 476 kHz).

To achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is

met. (A worst case minimum of 19 cycles is required.)

3. These values are hardwired into the Flash Controller’s state machine (tFTG =1/fFTG).

JTAG and Spy-Bi-Wire interface

PARAMETER

TEST

CONDITIONS

VCC

MIN

TYP

MAX

UNIT

fSBW

Spy-Bi-Wire input frequency

2.2 V/3 V

MHz

tSBW,Low

Spy-Bi-Wire low clock pulse length

2.2 V/3 V

0.025

tSBW,En

Spy-Bi-Wire enable time,

TEST high to acceptance of first clock edge

(see Note 1)

2.2 V/3 V

tSBW,Ret

Spy-Bi-Wire return to normal operation time

2.2 V/3 V

100

TCK input frequency (see Note 2)

2.2 V

MHz

fTCK

TCK input frequency (see Note 2)

MHz

RInternal

Internal pulldown resistance on TEST

2.2 V/3 V

k

NOTES: 1. Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin high

before applying the first SBWCLK clock edge.

2. fTCK may be restricted to meet the timing requirements of the module selected.

MSP430F4152IPM Datasheet(PDF) 49 Page - Texas Instruments

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